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| INTEGRATED CIRCUITS DATA SHEET SAA55xx Standard TV microcontrollers with On-Screen Display (OSD) Preliminary specification File under Integrated Circuits, IC02 1999 Oct 27 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) CONTENTS 1 2 3 4 5 6 6.1 6.2 7 7.1 8 8.1 8.2 8.3 8.4 8.5 8.6 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 11.4 12 12.1 12.2 12.3 12.4 13 14 14.1 15 15.1 15.2 15.3 16 16.1 17 17.1 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description MICROCONTROLLER Microcontroller features MEMORY ORGANISATION Security bits - program and verify RAM organisation Data memory SFR memory Character set feature bits External (auxiliary) memory POWER-ON RESET REDUCED POWER MODES Idle mode Power-down mode Standby mode I/O FACILITY I/O ports Port type Port alternate functions LED support INTERRUPT SYSTEM Interrupt enable structure Interrupt enable priority Interrupt vector address Level/edge interrupt TIMER/COUNTER WATCHDOG TIMER Watchdog Timer operation PULSE WIDTH MODULATORS PWM control Tuning Pulse Width Modulator (TPWM) Software ADC (SAD) I2C-BUS SERIAL I/O I2C-bus port selection MEMORY INTERFACE Memory structure 2 17.2 17.3 17.4 18 18.1 18.2 18.3 18.4 19 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 19.14 20 21 22 22.1 23 23.1 23.2 23.3 24 25 26 27 27.1 27.2 27.3 27.4 28 29 30 Memory mapping Addressing memory Page clearing DATA CAPTURE SAA55xx Data Capture Features Broadcast service data detection VPS acquisition WSS acquisition DISPLAY Display features Display mode Display feature descriptions Character and attribute coding Screen and global controls Screen colour Text display control Display positioning Character set Display synchronization Video/data switch (fast blanking) polarity Video/data switch adjustment RGB brightness control Contrast reduction MEMORY MAPPED REGISTERS LIMITING VALUES CHARACTERISTICS I2C-bus characteristics QUALITY AND RELIABILITY Group A Group B Group C APPLICATION INFORMATION ELECTROMAGNETIC COMPATIBILITY (EMC) GUIDELINES PACKAGE OUTLINE SOLDERING Introduction to soldering through-hole mount packages Soldering by dipping or by solder wave Manual soldering Suitability of through-hole mount IC packages for dipping and wave soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 1999 Oct 27 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 1 FEATURES SAA55xx * Single-chip microcontroller with integrated On-Screen Display (OSD) * Versions available with integrated data capture * One Time Programmable (OTP) memory for both program Read Only Memory (ROM) and character sets * Single power supply: 3.0 to 3.6 V * 5 V tolerant digital inputs and I/O * 29 I/O lines via individual addressable controls * Programmable I/O for push-pull, open-drain and quasi-bidirectional * Two port lines with 8 mA sink (at <0.4 V) capability, for direct drive of Light Emitting Diode (LED) * Single crystal oscillator for microcontroller, OSD and data capture * Power reduction modes: Idle and Power-down * Byte level I2C-bus with dual port I/O * Pin compatibility throughout family * Operating temperature: -20 to +70 C. 2 GENERAL DESCRIPTION The SAA55xx standard family of microcontrollers are a derivative of the Philips industry-standard 80C51 microcontroller, and are intended for use as the central control mechanism in a television receiver. They provide control functions for the television system, OSD, and some versions include an integrated data capture and display function. The data capture hardware has the capability of decoding and displaying both 525 and 625-line World System Teletext (WST), Video Programming System (VPS) and Wide Screen Signalling (WSS) information. The same display hardware is used both for Teletext and OSD, which means that the display features available give greater flexibility to differentiate the TV set. The SAA55xx standard family offers a range of functionality from non-text, 16-kbyte program ROM and 256-byte Random Access Memory (RAM), to a 10-page text version, 64-kbyte program ROM and 1.2-kbyte RAM. 3 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT Supply VDDX IDDP IDDC IDDC(id) IDDC(pd) IDDC(stb) IDDA IDDA(id) IDDA(pd) IDDA(stb) fxtal Tamb Tstg any supply voltage (VDD to VSS) periphery supply current core supply current Idle mode core supply current Power-down mode core supply current Standby mode core supply current analog supply current Idle mode analog supply current Power-down mode analog supply current Standby mode analog supply current crystal frequency operating ambient temperature storage temperature 3.0 1 - - - - - - - - - -20 -55 3.3 - 15 4.6 0.76 5.11 45 0.87 0.45 0.95 12 - - 3.6 - 18 6 1 6.50 48 1.0 0.7 1.20 - +70 +125 V mA mA mA mA mA mA mA mA mA MHz C C 1999 Oct 27 3 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 4 ORDERING INFORMATION PACKAGE(2) ROM NAME SAA5500PS/nnnn SAA5501PS/nnnn SAA5502PS/nnnn SAA5503PS/nnnn SAA5520PS/nnnn SAA5521PS/nnnn SAA5522PS/nnnn SAA5523PS/nnnn SAA5551PS/nnnn SAA5552PS/nnnn SAA5553PS/nnnn Notes 1. `nnnn' is a four digit number uniquely referencing the microcontroller program mask. 2. For details of the LQFP100 package, please contact your local regional office for availability. SDIP52 DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil) VERSION SOT247-1 16-kbyte 32-kbyte 48-kbyte 64-kbyte 16-kbyte 32-kbyte 48-kbyte 64-kbyte 32-kbyte 48-kbyte 64-kbyte SAA55xx TYPE NUMBER(1) RAM 256-byte 512-byte 256-byte 512-byte 256-byte 512-byte 750-byte 1-kbyte 750-byte 1-kbyte 1.2-kbyte TEXT PAGES - - - - 1 1 1 1 10 10 10 1999 Oct 27 4 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 5 BLOCK DIAGRAM SAA55xx handbook, full pagewidth I2C-bus, general I/O TV CONTROL AND INTERFACE ROM (16 TO 64-KBYTE) MICROPROCESSOR (80C51) SRAM (256-BYTE) DRAM (3 TO 12-KBYTE) MEMORY INTERFACE R CVBS DATA CAPTURE DISPLAY G B VDS CVBS DATA CAPTURE TIMING DISPLAY TIMING GSA029 VSYNC HSYNC Fig.1 Block diagram (top level architecture). 1999 Oct 27 5 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 6 6.1 PINNING INFORMATION Pinning SAA55xx handbook, halfpage P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 1 2 3 4 5 6 7 8 9 52 P1.5/SDA1 51 P1.4/SCL1 50 P1.7/SDA0 49 P1.6/SCL0 48 P1.3/T1 47 P1.2/INT0 46 P1.1/T0 45 P1.0/INT1 44 VDDP 43 RESET 42 XTALOUT 41 XTALIN 40 OSCGND P3.1/ADC1 10 P3.2/ADC2 11 P3.3/ADC3 12 VSSC 13 P0.0 14 P0.1 15 P0.2 16 P0.3 17 P0.4 18 P0.5 19 P0.6 20 P0.7 21 VSSA 22 CVBS0 23 CVBS1 24 SYNC_FILTER 25 IREF 26 MBK951 SAA55xx 39 VDDC 38 VSSP 37 VSYNC 36 HSYNC 35 VDS 34 R 33 G 32 B 31 VDDA 30 P3.4/PWM7 29 COR 28 VPE 27 FRAME Fig.2 SDIP52 pin configuration. 1999 Oct 27 6 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx 100 P2.0/TPWM 98 P2.6/PWM5 97 P2.5/PWM4 96 P2.4/PWM3 95 P2.3/PWM2 94 P2.2/PWM1 93 P2.1/PWM0 84 P1.5/SDA1 82 P1.7/SDA0 83 P1.4/SCL1 81 P1.6/SCL0 79 P1.2/INT0 handbook, full pagewidth P2.7/PWM6 P3.0/ADC0 n.c. P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 n.c. n.c. n.c. 1 2 3 4 5 6 7 8 9 76 P1.0/INT1 75 VDDP 74 n.c. 73 RESET 72 n.c. 71 XTALOUT 70 XTALIN 69 OSCGND 68 n.c. 67 n.c. 66 n.c. 65 n.c. 64 n.c. 63 VDDC 62 VPE_2 61 n.c. 60 VSSP 59 P3.6 58 n.c. 57 n.c. 56 n.c. 55 VSYNC 54 P3.5 53 HSYNC 52 VDS 51 n.c. n.c. 50 GSA001 80 P1.3/T1 78 P1.1/T0 R 48 99 n.c. 92 n.c. 91 n.c. 90 n.c. 89 n.c. 88 n.c. 87 n.c. 86 n.c. 85 n.c. n.c. 10 VSSC 11 VSSP 12 P0.5 13 n.c. 14 n.c. 15 P0.0 16 P0.1 17 P0.2 18 n.c. 19 n.c. 20 n.c. 21 P0.3 22 n.c. 23 P0.4 24 P3.7 25 n.c. 26 n.c. 27 P0.6 28 P0.7 29 VSSA 30 CVBS0 31 CVBS1 32 n.c. 33 SYNC_FILTER 34 IREF 35 n.c. 36 n.c. 37 n.c. 38 n.c. 39 n.c. 40 FRAME 41 VPE 42 COR 43 P3.4/PWM7 44 VDDA 45 B 46 G 47 n.c. 49 SAA55xx Fig.3 LQFP100 pin configuration. 1999 Oct 27 7 77 n.c. Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 6.2 Pin description SDIP52 and LQFP100 packages PIN SYMBOL SDIP52 P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 P3.4/PWM7 P3.5 P3.6 P3.7 VSSC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VSSA CVBS0 CVBS1 SYNC_FILTER IREF FRAME 1 2 3 4 5 6 7 8 9 10 11 12 30 - - - 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 LQFP100 100 93 94 95 96 97 98 1 2 4 5 6 44 54 59 25 11 16 17 18 22 24 13 28 29 30 31 32 34 35 41 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O - I I I I O analog ground core ground TYPE DESCRIPTION SAA55xx Table 1 Port 2. 8-bit programmable bidirectional port with alternative functions. P2.0/TPWM is the output for the 14-bit high precision PWM and P2.1/PWM0 to P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6. Port 3. 8-bit programmable bidirectional port with alternative functions. P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility and P3.4/PWM7 is the output for the 6-bit PWM7. P3.5 to P3.7 have no alternative functions and are only available with the LQFP100 package. Port 0. 8-bit programmable bidirectional port. P0.5 and P0.6 have 8 mA current sinking capability for direct drive of LEDs. Composite video input. A positive-going 1 V (peak-to-peak) input is required; connected via a 100 nF capacitor. CVBS sync filter input. This pin should be connected to VSSA via a 100 nF capacitor. Reference current input for analog circuits, connected to VSSA via a 24 k resistor. De-interlace output synchronized with the VSYNC pulse to produce a non-interlaced display by adjustment of the vertical deflection circuits. OTP programming voltage VPE 28 42 I 1999 Oct 27 8 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) PIN SYMBOL SDIP52 COR 29 LQFP100 43 O TYPE DESCRIPTION SAA55xx Open-drain, active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display. +3.3 V analog power supply Pixel rate output of the BLUE colour information. Pixel rate output of the GREEN colour information. Pixel rate output of the RED colour information. Video/data switch push-pull output for dot rate fast blanking. Schmitt triggered input for a TTL-level version of the horizontal sync pulse; the polarity of this pulse is programmable by register bit TXT1.H POLARITY. Schmitt triggered input for a TTL-level version of the vertical sync pulse; the polarity of this pulse is programmable by register bit TXT1.V POLARITY. periphery ground +3.3 V core power supply crystal oscillator ground 12 MHz crystal oscillator input 12 MHz crystal oscillator output If the reset input is HIGH for at least 2 machine cycles (24 oscillator periods) while the oscillator is running, the device is reset; this pin should be connected to VDDP via a capacitor. +3.3 V periphery power supply Port 1. 8-bit programmable bidirectional port with alternative functions. P1.0/INT1 is external interrupt 1 which can be triggered on the rising and falling edge of the pulse. P1.1/T0 is the counter/Timer 0. P1.2/INT0 is external interrupt 0. P1.3/T1 is the counter/Timer 1. P1.6/SCL0 is the serial clock input for the I2C-bus and P1.7/SDA0 is the serial data port for the I2C-bus. P1.4/SCL1 is the serial clock input for the I2C-bus. P1.5/SDA1 is the serial data port for the I2C-bus. OTP programming voltage not connected VDDA B G R VDS HSYNC 31 32 33 34 35 36 45 46 47 48 52 53 - O O O O I VSYNC 37 55 I VSSP VDDC OSCGND XTALIN XTALOUT RESET 38 39 40 41 42 43 12, 60 63 69 70 71 73 - - - I O I VDDP P1.0/INT1 P1.1/T0 P1.2/INT0 P1.3/T1 P1.6/SCL0 P1.7/SDA0 P1.4/SCL1 P1.5/SDA1 VPE_2 n.c. 44 45 46 47 48 49 50 51 52 - - 75 76 78 79 80 81 82 83 84 62 3, 7 to 10,14, 15, 19 to 21, 23, 26, 27, 33, 36 to 40, 49 to 51, 56 to 58, 61, 64 to 68, 72, 74, 77, 85 to 92, 99 - I/O I/O I/O I/O I/O I/O I/O I/O I - 1999 Oct 27 9 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 7 MICROCONTROLLER 8 MEMORY ORGANIZATION SAA55xx The functionality of the microcontroller used on this device is described here with reference to the industry standard 80C51 microcontroller. A full description of its functionality can be found in "Handbook IC20, 80C51-Based 8-bit Microcontrollers". 7.1 Microcontroller features The device has the capability of a maximum of 64-kbyte Program ROM and 1.2-kbyte Data RAM internally. 8.1 Security bits - program and verify * 80C51 microcontroller core standard instruction set and timing * 1 s machine cycle * Maximum 64K x 8-bit Program ROM * Maximum of 1.2K x 8-bit Auxiliary RAM * Interrupt Controller for individual enable/disable with two level priority * Two 16-bit Timer/Counter registers * Watchdog Timer * Auxiliary RAM page pointer * 16-bit Data pointer * Idle and Power-down modes * 29 general I/O lines * Eight 6-bit Pulse Width Modulator (PWM) outputs for control of TV analog signals * One 14-bit PWM for Voltage Synthesis Tuner (VST) control * 8-bit Analog-to-Digital Converter (ADC) with 4 multiplexed inputs * 2 high current outputs for directly driving LEDs * I2C-bus byte level bus interface with dual ports. SAA55xx devices have a set of security bits allied with each section of the device, i.e. Program ROM, Character ROM and Packet 26 ROM. The security bits are used to prevent the ROM from being overwritten once programmed, and also the contents being verified once programmed. The security bits are one-time programmable and cannot be erased. The SAA55xx memory and security bits are structured as shown in Fig.4. The SAA55xx security bits are set as shown in Fig.5 for production programmed devices and are set as shown in Fig.6 for production blank devices. 8.2 RAM organisation The internal Data RAM is organised into two areas, Data memory and Special Function Registers (SFRs) as shown in Fig.7. 8.3 Data memory The Data memory is 256 x 8-bit and occupies the address range 00H to FFH when using indirect addressing and 00H to 7FH when using direct addressing. The SFRs occupy the address range 80H to FFH and are accessible using direct addressing only. The lower 128 bytes of Data memory are mapped as shown in Fig.8. The lowest 24 bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable memory space. The upper 128 bytes are not allocated for any special area or functions. 1999 Oct 27 10 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx handbook, full pagewidth MEMORY SECURITY BITS INTERACTION USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) PROGRAM ROM USER ROM (64K x 8-BIT) CHARACTER ROM USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) USER ROM (9K x 12-BIT) PACKET 26 ROM USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) USER ROM (4K x 8-BIT) GSA030 Fig.4 Memory and security bit structures. handbook, full pagewidth MEMORY SECURITY BITS SET USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) ENABLED PROGRAM ROM DISABLED CHARACTER ROM DISABLED ENABLED PACKET 26 ROM DISABLED ENABLED MBK954 Fig.5 Security bits for production devices. 1999 Oct 27 11 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx handbook, full pagewidth MEMORY SECURITY BITS SET USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) ENABLED PROGRAM ROM ENABLED CHARACTER ROM ENABLED ENABLED PACKET 26 ROM ENABLED ENABLED MBK955 Fig.6 Security bits for production blank devices. handbook, halfpage DATA MEMORY SPECIAL FUNCTION REGISTERS FFH upper 128 bytes 80H 7FH lower 128 bytes 00H accessible by direct and indirect addressing MBK956 accessible by indirect addressing only accessible by direct addressing only Fig.7 Internal Data memory. 1999 Oct 27 12 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx handbook, halfpage 7FH 30H 2FH bit-addressable space (bit addresses 00H to 7FH) 20H 1FH 18H 17H 10H 0FH 08H 07H 0 4 banks of 8 registers (R0 to R7) R7 R0 R7 R0 R7 R0 R7 R0 MGM677 Fig.8 Lower 128 bytes of internal RAM. 1999 Oct 27 13 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 8.4 SFR memory 1999 Oct 27 14 Philips Semiconductors Standard TV microcontrollers with On-Screen Display (OSD) The Special Function Register (SFR) space is used for port latches, timer, peripheral control, acquisition control, display control. These registers can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. A summary of the SFR map in address order is shown in Table 2. A description of each of the SFR bits is shown in Table 3 which presents the SFRs in alphabetical order. Table 2 SFR memory map NAMES 7 P07 SP7 DPL7 DPH7 0 TF1 GATE TL07 TL17 TH07 TH17 P17 P0CFGA7 P0CFGB7 0 P1CFGA7 P1CFGB7 P27 P2CFGA7 P2CFGB7 EA P37 NOT3 TEN 0 6 P06 SP6 DPL6 DPH6 ARD TR1 C/T TL06 TL16 TH06 TH16 P16 P0CFGA6 P0CFGB6 0 P1CFGA6 P1CFGB6 P26 P2CFGA6 P2CFGB6 EBUSY P36 NOT2 TC2 0 5 P05 SP5 DPL5 DPH5 RFI TF0 M1 TL05 TL15 TH05 TH15 P15 P0CFGA5 P0CFGB5 0 P1CFGA5 P1CFGB5 P25 P2CFGA5 P2CFGB5 ES2 P35 NOT1 TC1 0 4 P04 SP4 DPL4 DPH4 WLE TR0 M0 TL04 TL14 TH04 TH14 P14 P0CFGA4 P0CFGB4 DC_COMP P1CFGA4 P1CFGB4 P24 P2CFGA4 P2CFGB4 - P34 NOT0 TC0 0 3 P03 SP3 DPL3 DPH3 GF1 IE1 GATE TL03 TL13 TH03 TH13 P13 P0CFGA3 P0CFGB3 SAD3 P1CFGA3 P1CFGB3 P23 P2CFGA3 P2CFGB3 ET1 P33 0 0 OSD LANG ENABLE 2 P02 SP2 DPL2 DPH2 GF0 IT1 C/T TL02 TL12 TH02 TH12 P12 P0CFGA2 P0CFGB2 SAD2 P1CFGA2 P1CFGB2 P22 P2CFGA2 P2CFGB2 EX1 P32 0 0 OSD LAN2 1 P01 SP1 DPL1 DPH1 PD IE0 M1 TL01 TL11 TH01 TH11 P11 P0CFGA1 P0CFGB1 SAD1 P1CFGA1 P1CFGB1 P21 P2CFGA1 P2CFGB1 ET0 P31 BS1 TS1 OSD LAN1 0 P00 SP0 DPL0 DPH0 IDL IT0 M0 TL00 TL10 TH00 TH10 P10 P0CFGA0 P0CFGB0 SAD0 P1CFGA0 P1CFGB0 P20 P2CFGA0 P2CFGB0 EX0 P30 BS0 TS0 OSD LAN0 RESET FFH 07H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH FFH 00H 00H FFH 00H FFH FFH ADD R/W 80H 81H 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 90H 96H 97H 98H 9EH 9FH A0H A6H A7H A8H B0H B2H B3H B4H R/W P0 R/W SP R/W DPL R/W DPH R/W PCON R/W TCON R/W TMOD R/W TL0 R/W TL1 R/W TH0 R/W TH1 R/W P1 R/W P0CFGA R/W P0CFGB R/W SADB R/W P1CFGA R/W P1CFGB R/W P2 R/W P2CFGA R/W P2CFGB R/W IE R/W P3 R/W TXT18 R/W TXT19 R/W TXT20 Preliminary specification 00H 00H SAA55xx FFH 00H 00H 00H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Oct 27 15 Philips Semiconductors ADD R/W B5H B6H B8H B9H R NAMES TXT22 7 0 GPF7 0 0 0 0 WSS<13:11> ERROR 1 0 X24 POSN 6 0 GPF6 PBUSY FORCE ACQ1 0 0 WSS13 1 0 DISPLAY X24 8-BIT REQ3 - QUAD WIDTH ENABLE 5 0 0 PES2 FORCE ACQ0 0 0 WSS12 1 0 AUTO FRAME ACQ OFF REQ2 - EAST/WEST 4 0 GPF4 PCC FORCE DISP1 WSS<3:0> ERROR WSS<7:4> ERROR WSS11 P3CFGA4 P3CFGB4 DISABLE HEADER ROLL X26 OFF REQ1 PRD4 DISABLE DOUBLE HEIGHT COR IN COR IN BOTTOM /TOP DISABLE SPANISH R4 C4 D4 I2C 3 PORT 1 PT1 FORCE DISP0 WSS3 WSS7 WSS<10:8> ERROR P3CFGA3 P3CFGB3 DISPLAY STATUS ROW ONLY FULL FIELD REQ0 PRD3 B MESH ENABLE TEXT OUT TEXT OUT DOUBLE HEIGHT PKT 26 RECEIVED R3 C3 D3 GPF3 2 0 0 PX1 SCREEN COL2 WSS2 WSS6 WSS10 P3CFGA2 P3CFGB2 DISABLE FRAME FIELD POLARITY SC2 PRD2 C MESH ENABLE TEXT IN TEXT IN BOX ON 24 WSS RECEIVED R2 C2 D2 I2C 1 PORT 0 PT0 SCREEN COL1 WSS1 WSS5 WSS9 P3CFGA1 P3CFGB1 VPS ON GPF1 0 0 GPF0 PX0 SCREEN COL0 WSS0 WSS4 WSS8 P3CFGA0 P3CFGB0 INV ON RESET 02H XXH 00H 00H 00H 00H 00H FFH 00H 00H Standard TV microcontrollers with On-Screen Display (OSD) R/W TXT21 R/W IP R/W TXT17 WSS1 WSS2 WSS3 BAH R BBH R BCH R BEH R/W P3CFGA BFH C0H R/W P3CFGB R/W TXT0 C1H C2H C3H C4H R/W TXT1 R/W TXT2 W TXT3 R/W TXT4 EXT PKT OFF ACQ BANK - OSD BANK ENABLE H POLARITY SC1 PRD1 TRANS ENABLE PICTURE ON OUT PICTURE ON OUT BOX ON 1 - 23 WSS ON R1 C1 D1 V POLARITY SC0 PRD0 SHADOW ENABLE PICTURE ON IN PICTURE ON IN BOX ON 0 CVBS1/ CVBS0 R0 C0 D0 00H 00H 00H 00H C5H C6H C7H C8H C9H R/W TXT5 R/W TXT6 R/W TXT7 R/W TXT8 R/W TXT9 BKGND OUT BKGND IN BKGND OUT BKGND IN STATUS ROW TOP (reserved) 0 CURSOR FREEZE 0 D7 CURSOR ON FLICKER STOP ON CLEAR MEMORY 0 D6 COR OUT COR OUT REVEAL (reserved) 0 A0 C5 D5 03H 03H 00H 00H Preliminary specification SAA55xx 00H 00H 00H CAH R/W TXT10 CBH R/W TXT11 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Oct 27 16 Philips Semiconductors ADD R/W CCH R NAMES TXT12 7 525/625 SYNC 0 0 C TD7 TPWE PW7E PW0E PW1E CR2 STAT4 DAT7 ADR6 PW3E PW4E PW5E PW6E ACC7 PW2E VHI B7 VPS RECEIVED XRAMP7 STANDBY WKEY7 WDV7 6 SPANISH 5 ROM VER3 4 ROM VER2 3 ROM VER1 2 ROM VER0 1 1 0 VIDEO SIGNAL QUALITY PAGE0 BLOCK0 P TD0 TD8 PW7V0 PW0V0 PW1V0 CR0 0 DAT0 GC PW3V0 PW4V0 PW5V0 PW6V0 ACC0 PW2V0 SAD4 B0 0 XRAMP0 (reserved) 0 WKEY0 WDV0 RESET XXXX XX1X 00H 00H 00H 00H 40H 40H 40H 40H 00H F8H 00H 00H 40H 40H 40H 40H 00H 40H 00H 00H XXXX XXX0 00H Preliminary specification 00H 00H 00H Standard TV microcontrollers with On-Screen Display (OSD) CDH R/W TXT14 CEH R/W TXT15 D0H D2H D3H D4H D5H D6H D8H D9H R/W PSW R/W TDACL R/W TDACH R/W PWM7 R/W PWM0 R/W PWM1 R/W S1CON R S1STA 0 0 AC TD6 1 1 1 1 ENSI STAT3 DAT6 ADR5 1 1 1 1 ACC6 1 CH1 B6 0 0 F0 TD5 TD13 PW7V5 PW0V5 PW1V5 STA STAT2 DAT5 ADR4 PW3V5 PW4V5 PW5V5 PW6V5 ACC5 PW2V5 CH0 B5 - - RS1 TD4 TD12 PW7V4 PW0V4 PW1V4 STO STAT1 DAT4 ADR3 PW3V4 PW4V4 PW5V4 PW6V4 ACC4 PW2V4 ST B4 525 TEXT XRAMP4 0 WKEY4 WDV4 PAGE3 BLOCK3 RS0 TD3 TD11 PW7V3 PW0V3 PW1V3 SI STAT0 DAT3 ADR2 PW3V3 PW4V3 PW5V3 PW6V3 ACC3 PW2V3 SAD7 B3 625 TEXT XRAMP3 0 WKEY3 WDV3 PAGE2 BLOCK2 OV TD2 TD10 PW7V2 PW0V2 PW1V2 AA 0 DAT2 ADR1 PW3V2 PW4V2 PW5V2 PW6V2 ACC2 PW2V2 SAD6 B2 PKT 8/30 XRAMP2 0 WKEY2 WDV2 PAGE1 BLOCK1 - TD1 TD9 PW7V1 PW0V1 PW1V1 CR1 0 DAT1 ADR0 PW3V1 PW4V1 PW5V1 PW6V1 ACC1 PW2V1 SAD5 B1 FASTEXT XRAMP1 (reserved) 0 WKEY1 WDV1 DAH R/W S1DAT DBH R/W S1ADR DCH R/W PWM3 DDH R/W PWM4 DEH R/W PWM5 DFH R/W PWM6 E0H E4H E8H F0H F8H R/W ACC R/W PWM2 R/W SAD R/W B R/W TXT13 PAGE 525 DISPLAY CLEARING XRAMP6 0 WKEY6 WDV6 XRAMP5 0 WKEY5 WDV5 FAH R/W XRAMP FBH R/W ROMBK FEH FFH W WDTKEY SAA55xx R/W WDT Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) Table 3 SFR bit description BIT Accumulator (ACC) ACC7 to ACC0 B Register (B) B7 to B0 Data Pointer High byte (DPH) DPH7 to DPH0 Data Pointer Low byte (DPL) DPL7 to DPL0 Interrupt Enable Register (IE) EA EBUSY ES2 ET1 EX1 ET0 EX0 Interrupt Priority Register (IP) PBUSY PES2 PCC PT1 PX1 PT0 PX0 Port 0 (P0) P07 to P00 Port 1 (P1) P17 to P10 Port 2 (P2) P27 to P20 Port 3 (P3) P37 to P30 Port 2 I/O register connected to external pins Port 1 I/O register connected to external pins Port 0 I/O register connected to external pins priority EBUSY interrupt priority ES2 interrupt priority ECC interrupt priority Timer 1 interrupt priority external interrupt 1 priority Timer 0 interrupt priority external interrupt 0 B register value accumulator value FUNCTION SAA55xx data pointer high byte, used with DPL to address auxiliary memory data pointer low byte, used with DPH to address auxiliary memory disable all interrupts (logic 0), or use individual interrupt enable bits (logic 1) enable BUSY interrupt enable I2C-bus interrupt enable Timer 1 interrupt enable external interrupt 1 enable Timer 0 interrupt enable external interrupt 0 Port 3 I/O register connected to external pins; P37 to P35 are only available with the LQFP100 package 1999 Oct 27 17 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) BIT FUNCTION SAA55xx Port 0 Configuration A (P0CFGA) and Port 0 Configuration B (P0CFGB) P0CFGA<7:0> and P0CFGB<7:0> These two registers are used to configure Port 0 pins. For example, the configuration of Port 0 pin 3 is controlled by setting bit 3 in both P0CFGA and P0CFGB. P0CFGB 1999 Oct 27 18 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) BIT Power Control Register (PCON) ARD RFI WLE GF1 GF0 PD IDL Program Status Word (PSW) C AC F0 RS1 to RS0 carry bit auxiliary carry bit flag 0 register bank selector bits RS<1:0>: 00 = Bank 0 (00H to 07H) 01 = Bank 1 (08H to 0FH) 10 = Bank 2 (10H to 17H) 11 = Bank 3 (18H to 1FH) OV P overflow flag parity bit FUNCTION SAA55xx auxiliary RAM disable bit, all MOVX instructions access the external data memory disable ALE during internal access to reduce radio frequency interference Watchdog Timer enable general purpose flag 1 general purpose flag 0 Power-down mode activation bit Idle mode activation bit Pulse Width Modulator 0 Control Register (PWM0) PW0E PW0V5 to PW0V0 activate this PWM and take control of respective port pin (logic 1) pulse width modulator high time Pulse Width Modulator 1 Control Register (PWM1) PW1E PW1V5 to PW1V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 2 Control Register (PWM2) PW2E PW2V5 to PW2V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 3 Control Register (PWM3) PW3E PW3V5 to PW3V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 4 Control Register (PWM4) PW4E PW4V5 to PW4V0 activate this PWM (logic 1) pulse width modulator high time 1999 Oct 27 19 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) BIT Pulse Width Modulator 5 Control Register (PWM5) PW5E PW5V5 to PW5V0 activate this PWM (logic 1) pulse width modulator high time FUNCTION SAA55xx Pulse Width Modulator 6 Control Register (PWM6) PW6E PW6V5 to PW6V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 7 Control Register (PWM7) PW7E PW7V5 to PW7V0 ROM Bank (ROMBK) STANDBY standby activation bit activate this PWM (logic 1) pulse width modulator high time I2C-bus Slave Address Register (S1ADR) ADR6 to ADR0 GC I2C-bus Control Register (S1CON) CR2 to CR0 clock rate bits; CR<2:0>: 000 = 100 kHz bit rate 001 = 3.75 kHz bit rate 010 = 150 kHz bit rate 011 = 200 kHz bit rate 100 = 25 kHz bit rate 101 = 1.875 kHz bit rate 110 = 37.5 kHz bit rate 111 = 50 kHz bit rate ENSI STA enable I2C-bus interface (logic 1) START flag. When this bit is set in slave mode, the hardware checks the I2C-bus and generates a START condition if the bus is free or after the bus becomes free. If the device operates in master mode it will generate a repeated START condition. STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C-bus clears this bit. This bit may also be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C-bus, but the hardware releases the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware. I2C-bus slave address to which the device will respond enable I2C-bus general call address (logic 1) STO 1999 Oct 27 20 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) BIT SI FUNCTION SAA55xx Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur: * A START condition is generated in master mode * The own slave address has been received during AA = 1 * The general call address has been received while S1ADR.GC and AA = 1 * A data byte has been received or transmitted in master mode (even if arbitration is lost) * A data byte has been received or transmitted as selected slave * A STOP or START condition is received as selected slave receiver or transmitter. While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset by software. AA Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions: * Own slave address is received * General call address is received (S1ADR.GC = 1) * A data byte is received, while the device is programmed to be a master receiver * A data byte is received, while the device is selected slave receiver. When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received. I2C-bus Data Register (S1DAT) DAT7 to DAT0 I2C-bus Status Register (S1STA) STAT4 to STAT0 Software ADC Register (SAD) VHI CH1 to CH0 analog input voltage greater than DAC voltage (logic 1) ADC input channel select bits; CH<1:0>: 00 = ADC3 01 = ADC0 10 = ADC1 11 = ADC2 ST(1) SAD7 to SAD4 initiate voltage comparison between ADC input channel and SAD value 4 MSBs of DAC input word I2C-bus interface status I2C-bus data Software ADC Control Register (SADB) DC_COMP SAD3 to SAD0 Stack Pointer (SP) SP7 to SP0 stack pointer value enable DC comparator mode (logic 1) 4 LSBs of SAD value 1999 Oct 27 21 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) BIT Timer/Counter Control Register (TCON) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 FUNCTION SAA55xx Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn timer/counter on/off. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 run control bit. Set/cleared by software to turn timer/counter on/off. Interrupt 1 Edge flag. Both edges generate flag. Set by hardware when external interrupt edge detected. Cleared by hardware when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify edge/LOW level triggered external interrupts. Interrupt 0 Edge l flag. Set by hardware when external interrupt edge detected. Cleared by hardware when interrupt processed. Interrupt 0 type flag. Set/cleared by software to specify falling edge/LOW level triggered external interrupts. 14-bit PWM MSB Register (TDACH) TPWE TD13 to TD8 14-bit PWM LSB Register (TDACL) TD7 to TD0 Timer 0 High byte (TH0) TH07 to TH00 Timer 1 High byte (TH1) TH17 to TH10 Timer 0 Low byte (TL0) TL07 to TL00 Timer 1 Low byte (TL1) TL17 to TL10 8 LSBs of Timer 1 16-bit counter 8 LSBs of Timer 0 16-bit counter 8 MSBs of Timer 1 16-bit counter 8 MSBs of Timer 0 16-bit counter 8 LSBs of 14-bit number to be output by the 14-bit PWM activate this 14-bit PWM (logic 1) 6 MSBs of 14-bit number to be output by the 14-bit PWM Timer/Counter Mode Control (TMOD) GATE C/T M1 to M0 gating control Timer/Counter 1 Counter/Timer 1 selector mode control bits timer/counter 1; M<1:0>: 00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler 01 = 16-bit time interval or event counter 10 = 8-bit time interval or event counter with automatic reload upon overflow; reload value stored in TH1 11 = stopped GATE C/T Gating control Timer/Counter 0 Counter/Timer 0 selector 1999 Oct 27 22 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) BIT M1 to M0 FUNCTION mode control bits timer/counter 0; M<1:0>: 00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler 01 = 16-bit time interval or event counter SAA55xx 10 = 8-bit time interval or event counter with automatic reload upon overflow; reload value stored in TH0 11 = one 8-bit time interval or event counter and one 8-bit time interval counter Text Register 0 (TXT0) X24 POSN DISPLAY X24 AUTO FRAME DISABLE HEADER ROLL DISPLAY STATUS ROW ONLY DISABLE FRAME VPS ON INV ON Text Register 1 (TXT1) EXT PKT OFF 8-BIT ACQ OFF X26 OFF FULL FIELD FIELD POLARITY H POLARITY V POLARITY Text Register 2 (TXT2) ACQ BANK REQ3 to REQ0 SC2 to SC0 Text Register 3 (TXT3) PRD4 to PRD0 Text Register 4 (TXT4) OSD BANK ENABLE QUAD WIDTH ENABLE EAST/WEST DISABLE DOUBLE HEIGHT B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE 1999 Oct 27 alternate OSD location available via graphic attribute, additional 32 locations (logic 1) enable display of quadruple width characters (logic 1) eastern language selection of character codes A0H to FFH (logic 1) disable normal decoding of double height characters (logic 1) enable meshing of black background (logic 1) enable meshing of coloured background (logic 1) display black background as video (logic 1) display shadow/fringe (default SE black) (logic 1) 23 page request data select acquisition Bank 1 (logic 1) page request start column of page request disable acquisition of extension packets (logic 1) disable checking of packets 0 to 24 written into memory (logic 1) disable writing of data into Display memory (logic 1) disable automatic processing of X/26 data (logic 1) acquire data on any TV line (logic 1) VSYNC pulse in second half of line during even field (logic 1) HSYNC reference edge is negative going (logic 1) VSYNC reference edge is negative going (logic 1) store packet 24 in extension packet memory (logic 0) or page memory (logic 1) display X24 from page memory (logic 0) or extension packet memory (logic 1) FRAME output switched off automatically if any video displayed (logic 1) disable writing of rolling headers and time into memory (logic 1) display row 24 only (logic 1) FRAME output always LOW (logic 1) enable capture of VPS data (logic 1) enable capture of inventory page in block 8 (logic 1) Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) BIT Text Register 5 (TXT5) BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN Text Register 6 (TXT6) BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN Text Register 7 (TXT7) STATUS ROW TOP CURSOR ON REVEAL BOTTOM/TOP DOUBLE HEIGHT BOX ON 24 BOX ON 1 to 23 BOX ON 0 Text Register 8 (TXT8) FLICKER STOP ON DISABLE SPANISH PKT 26 WSS RECEIVED(2) RECEIVED(2) disable `Flicker Stopper' circuitry (logic 1) background colour displayed outside teletext boxes (logic 1) background colour displayed inside teletext boxes (logic 1) COR active outside teletext and OSD boxes (logic 1) COR active inside teletext and OSD boxes (logic 1) text displayed outside teletext boxes (logic 1) text displayed inside teletext boxes (logic 1) video displayed outside teletext boxes (logic 1) video displayed inside teletext boxes (logic 1) background colour displayed outside teletext boxes (logic 1) background colour displayed inside teletext boxes (logic 1) COR active outside teletext and OSD boxes (logic 1) COR active inside teletext and OSD boxes (logic 1) text displayed outside teletext boxes (logic 1) text displayed inside teletext boxes (logic 1) video displayed outside teletext boxes (logic 1) video displayed inside teletext boxes (logic 1) FUNCTION SAA55xx display memory row 24 information above teletext page (on display row 0) (logic 1) display cursor at position given by TXT9 and TXT10 (logic 1) display characters in area with conceal attribute set (logic 1) display memory rows 12 to 23 when DOUBLE HEIGHT height bit is set (logic 1) display each character as twice normal height (logic 1) enable display of teletext boxes in memory row 24 (logic 1) enable display of teletext boxes in memory row 1 to 23 (logic 1) enable display of teletext boxes in memory row 0 (logic 1) disable special treatment of Spanish packet 26 characters (logic 1) packet 26 data has been processed (logic 1) WSS data has been processed (logic 1) enable acquisition of WSS data (logic 1) select CVBS1 as source for device (logic 1) WSS ON CVBS1/CVBS0 1999 Oct 27 24 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) BIT Text Register 9 (TXT9) CURSOR FREEZE CLEAR MEMORY(1) A0 R4 to R0(3) Text Register 10 (TXT10) C5 to C0(4) Text Register 11 (TXT11) D7 to D0 Text Register 12 (TXT12) 625/525 SYNC SPANISH ROM VER3 to ROM VER0 VIDEO SIGNAL QUALITY Text Register 13 (TXT13) VPS RECEIVED PAGE CLEARING 525 DISPLAY 525 TEXT 625 TEXT PKT 8/30 FASTEXT Text Register 14 (TXT14) PAGE3 to PAGE0 Text Register 15 (TXT15) BLOCK3 to BLOCK0 Text Register 17 (TXT17) FORCE ACQ1 to FORCE ACQ0 FORCE ACQ<1:0>: 00 = automatic selection 01 = force 525 timing, force 525 teletext standard 10 = force 625 timing, force 625 teletext standard 11 = force 625 timing, force 525 teletext standard FORCE DISP1 to FORCE DISP0 FORCE DISP<1:0>: 00 = automatic selection 01 = force display to 525 mode (9 lines per row) 10 = force display to 625 mode (10 lines per row) 11 = not valid (default to 625 mode) current micro block to be accessed by TXT9, TXT10 and TXT11 current display page VPS data (logic 1) software or power-on page clear in progress (logic 1) 525-line synchronisation for display (logic 1) 525-line WST being received (logic 1) 625-line WST being received (logic 1) packet 8/30/x(625) or packet 4/30/x(525) data detected (logic 1) packet x/27 data detected (logic 1) 525-line CVBS signal is being received (logic 1) Spanish character set present (logic 1) mask programmable identification for character set acquisition can be synchronized to CVBS (logic 1) current memory column value lock cursor at current position (logic 1) clear memory block pointed to by TXT15 (logic 1) access extension packet memory (logic 1) current memory row value FUNCTION SAA55xx data value written or read from memory location defined by TXT9, TXT10 and TXT15 1999 Oct 27 25 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) BIT FUNCTION SAA55xx SCREEN COL2 to SCREEN COL0 Defines colour to be displayed instead of TV picture and black background; these bits are equivalent to the RGB components. SCREEN COL<2:0>: 000 = transparent 001 = CLUT entry 9 010 = CLUT entry 10 011 = CLUT entry 11 100 = CLUT entry 12 101 = CLUT entry 13 110 = CLUT entry 14 111 = CLUT entry 15 Text Register 18 (TXT18) NOT3 to NOT0 BS1 to BS0 Text Register 19 (TXT19) TEN TC2 to TC0 TS1 to TS0 Text Register 20 (TXT20) OSD LANG ENABLE OSD LAN2 to OSD LAN0 Text Register 21 (TXT21) I2C PORT 1 I2C PORT 0 Text Register 22 (TXT22) GPF7 to GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0 Watchdog Timer (WDT) WDV7 to WDV0 Watchdog Timer period reserved standard device (logic 0) 10 pages available (logic 1) PWM0, PWM1, PWM2 and PWM3 outputs routed to Port 2.1 to Port 2.4 respectively (logic 1) reserved text acquisition available (logic 1) reserved enable I2C-bus Port 1 selection (P1.5/SDA1 and P1.4/SCL1) (logic 1) enable I2C-bus Port 0 selection (P1.7/SDA0 and P1.6/SCL0) (logic 1) enable use of OSD LAN<2:0> to define language option for display, instead of C12, C13 and C14 alternative C12, C13 and C14 bits for use with OSD menus enable twist character set (logic 1) language control bits (C12, C13 and C14) that has twisted character set twist character set selection national option table selection, maximum of 31 when used with EAST/WEST bit basic character set selection 1999 Oct 27 26 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) BIT Watchdog Timer Key (WDTKEY) WKEY7 to WKEY0(5) Wide Screen Signalling 1 (WSS1) WSS<3:0> ERROR WSS3 to WSS0 Wide Screen Signalling 2 (WSS2) WSS<7:4> ERROR WSS7 to WSS4 Wide Screen Signalling 3 (WSS3) WSS<13:11> ERROR WSS13 to WSS11 WSS<10:8> ERROR WSS10 to WSS8 XRAMP XRAMP7 to XRAMP0 Notes 1. This flag is set by software and reset by hardware. 2. This flag is set by hardware and must be reset by software. 3. Valid range TXT mode 0 to 24. 4. Valid range TXT mode 0 to 39. 5. Must be set to 55H to disable Watchdog Timer when active. internal RAM access upper byte address error in WSS<13:11> (logic 1) signalling bits to define reserved elements (group 4) error in WSS<10:8> (logic 1) signalling bits to define subtitles (group 3) error in WSS<7:4> (logic 1) signalling bits to define enhanced services (group 2) error in WSS<3:0> (logic 1) signalling bits to define aspect ratio (group 1) Watchdog Timer Key FUNCTION SAA55xx 1999 Oct 27 27 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 8.5 Character set feature bits SAA55xx Features available on the SAA55xx devices are reflected in a specific area of the character ROM. These sections of the character ROM are mapped to two Special Function Registers: TXT22 and TXT12. Character ROM address 09FEH is mapped to SFR TXT22 as shown in Table 4. Character ROM address 09FFH is mapped to SFR TXT12 as shown in Table 6. Table 4 Character ROM - TXT22 mapping U = used; X = reserved MAPPED ITEMS Character ROM address 09FEH Mapped to TXT22 Table 5 11 X - 10 X - 9 X - 8 X - 7 X 7 6 X 6 5 U 5 4 U 4 3 U 3 2 X 2 1 U 1 0 X 0 Description of Character ROM address 09FEH bits FUNCTION reserved; normally set to logic 1 1 = Text Acquisition available 0 = Text Acquisition not available reserved 1 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 2.1 to Port 2.4 respectively 0 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 3.0 to Port 3.3 respectively 1 = 10 page available 0 = 6 page available 0 = standard device reserved; normally set to logic 1 BIT NUMBER 0 1 2 3 4 5 6 to 11 Table 6 Character ROM - TXT12 mapping U = used; X = reserved MAPPED ITEMS Character ROM address 09FFH Mapped to TXT12 Table 7 11 X - 10 X - 9 X - 8 X - 7 X - 6 X - 5 X - 4 U 6 3 X 5 2 X 4 1 X 3 0 X 2 Description of Character ROM address 09FFH bits FUNCTION 1 = Spanish character set present 0 = no Spanish character set present reserved; normally set to logic 1 BIT NUMBER 4 0 to 3, 5 to 11 1999 Oct 27 28 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 8.6 External (auxiliary) memory 8.6.1 AUXILIARY RAM PAGE SELECTION SAA55xx The normal 80C51 external memory area has been mapped internally to the device, this means that the MOVX instruction accesses memory internal to the device. The Auxiliary RAM page pointer is used to select one of the 256 pages within the Auxiliary RAM, not all pages are allocated, refer to Fig.10 for further detail. A page consists of 256 consecutive bytes. handbook, halfpage 7FFFH FFFFH 4800H 47FFH DISPLAY RAM FOR TEXT PAGES (2) 2000H 1FFFH 500H 4FFH DATA RAM (1) 0000H 8700H GSA031 8C00H 87FFH DISPLAY REGISTERS 87F0H 871FH CLUT lower 32 kbytes (1) Amount of Data RAM depends on the device. (2) Amount of Display RAM depends on the device. upper 32 kbytes Fig.9 Auxiliary RAM allocation. 1999 Oct 27 29 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx handbook, full pagewidth FFH 00H FFH 00H MOVX @ Ri,A MOVX A, @ Ri FFH 00H FFH 00H SFR XRAMP = 00H MBK958 FFFFH SFR XRAMP = FFH FF00H FEFFH SFR XRAMP = FEH FE00H MOVX @ DPTR,A MOVX A, @ DPTR 01FFH SFR XRAMP = 01H 0100H 00FFH 0000H Fig.10 Indirect addressing of Auxiliary RAM. 9 POWER-ON RESET An automatic reset can be obtained when VDD is turned on by connecting the RESET pin to VDDP through a 10 F capacitor, providing the VDD rise time does not exceed 1 ms, and the oscillator start-up time does not exceed 10 ms. To ensure correct initialisation, the RESET pin must be held high long enough for the oscillator to settle following power-up, usually a few ms. Once the oscillator is stable, a further 24 clocks are required to generate the reset (two machine cycles of the microcontroller). Once the above reset condition has been detected an internal reset signal is triggered which remains active for 2048 clock cycles. 1999 Oct 27 30 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 10 REDUCED POWER MODES There are two power saving modes, Idle and Power-down, incorporated into the 10 page devices. There is an additional Standby mode incorporated into the 1 page devices. When utilizing any mode, power to the device (VDDP, VDDC and VDDA) should be maintained, since power saving is achieved by clock gating on a section by section basis. 10.1 Idle mode SAA55xx * The third method of terminating Idle mode is with an external hardware reset. Since the oscillator is running, the hardware reset need only be active for two machine cycles (24 clocks at 12 MHz) to complete the reset operation. Reset defines all SFRs and Display memory to an initialized state, but maintains all other RAM values. Code execution commences with the Program Counter set to `0000'. 10.2 Power-down mode During Idle mode, Acquisition, Display and the Central Processing Unit (CPU) sections of the device are disabled. The following functions remain active: * Memory interface * I2C-bus interface * Timer/Counters * Watchdog Timer * Pulse Width Modulators. To enter Idle mode the IDL bit in the PCON register must be set. The Watchdog Timer must be disabled prior to entering the Idle mode to prevent the device being reset. Once in Idle mode, the crystal oscillator continues to run, but the internal clock to the CPU, Acquisition and Display are gated out. However, the clocks to the Memory interface, I2C-bus interface, Timer/Counters, Watchdog Timer and Pulse Width Modulators are maintained. The CPU state is frozen along with the status of all SFRs, internal RAM contents are maintained, as are the device output pin values. Since the output values on Red Green Blue (RGB) and the Video Data Switch (VDS) are maintained the display output must be disabled before entering this mode. There are three methods to recover from Idle mode: * Assertion of an enabled interrupt will cause the IDL bit to be cleared by hardware, thus terminating Idle mode. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Idle mode. * A second method of exiting the Idle mode is via an interrupt generated by the SAD DC Compare circuit. When the device is configured in this mode, detection of an analog threshold at the input to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device into Idle mode. In Power-down mode the crystal oscillator is stopped. The contents of all SFRs and Data memory are maintained, However, the contents of the Auxiliary/Display memory are lost. The port pins maintain the values defined by their associated SFRs. Since the output values on RGB and VDS are maintained the display output must be made inactive before entering Power-down mode. The Power-down mode is activated by setting the PD bit in the PCON register. It is advised to disable the Watchdog Timer prior to entering power-down. There are three methods of exiting power-down: * An external interrupt provides the first mechanism for waking from power-down. Since the clock is stopped, external interrupts needs to be set level sensitive prior to entering power-down. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Power-down mode. * A second method of exiting power-down is via an interrupt generated by the SAD DC Compare circuit. When the device is configured in this mode, detection of a certain analog threshold at the input to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device into power-down. * The third method of terminating the Power-down mode is with an external hardware reset. Reset defines all SFRs and Display memory, but maintains all other RAM values. Code execution commences with the Program Counter set to `0000'. 1999 Oct 27 31 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 10.3 Standby mode 11.2.1 OPEN-DRAIN SAA55xx This mode is only available on 1 page devices. When Standby mode is entered both Acquisition and Display sections are disabled. The following functions remain active: * 80C51 core * Memory interface * I2C-bus interface * Timer/Counters * Watchdog Timer * Software ADC * Pulse Width Modulators. To enter Standby mode, the STANDBY control bit in the ROMBK SFR (bit 7) must be set. It can be used in conjunction with either Idle or Power-down modes to switch between power saving modes. This mode enables the 80C51 core to decode either IR remote commands or receive I2C-bus commands without the device being fully powered. The Standby state is maintained upon exit from either the Idle mode or Power-down mode. No wake-up from Standby is necessary as the 80C51 core remains operational. Since the output values on RGB and VDS are maintained the display output must be disabled before entering this mode. 11 I/O FACILITY 11.1 I/O ports The open-drain configuration can be used for bidirectional operation of a port. It requires an external pull-up resistor, the pull-up voltage has a maximum value of 5.5 V, to allow connection of the device into a 5 V environment. The I2C-bus ports (P1.4,P1.5, P1.6 and P1.7) can only be configured as open-drain. 11.2.2 QUASI-BIDIRECTIONAL The quasi-bidirectional configuration is a combination of open-drain and push-pull. It requires an external pull-up resistor to VDDP (nominally 3.3 V). When a signal transition from LOW-to-HIGH is output from the device, the pad is put into push-pull configuration for one clock cycle (166 ns) after which the pad goes into open-drain configuration. This configuration is used to speed up the edges of signal transitions. This is the default mode of operation of the pads after reset. 11.2.3 HIGH-IMPEDANCE The high-impedance configuration can be used for input only operation of the port. When using this configuration the two output transistors are turned off. 11.2.4 PUSH-PULL The push-pull configuration can be used for output only. In this mode the signal is driven to either 0 V or VDDP, which is nominally 3.3 V. 11.3 Port alternate functions The SAA55xx devices have 29 I/O lines, each is individually addressable, or form three parallel 8-bit addressable ports which are Port 0, Port 1 and Port 2. Port 3 has 5-bit parallel I/O only. 11.2 Port type Ports 1, 2 and 3 are shared with alternative functions to enable control of external devices and circuitry. The alternative functions are enabled by setting the appropriate SFR and also writing a logic 1 to the port bit that the function occupies. 11.4 LED support All individual ports can be programmed to function in one of four I/O configurations: open-drain, quasi-bidirectional, high-impedance and push-pull. The I/O configuration is selected using two associated Port Configuration Registers: PnCFGA and PnCFGB (where n = port number 0, 1, 2 or 3); see Table 3. Port pins P0.5 and P0.6 have a 8 mA current sinking capability to enable LEDs in series with current limiting resistors to be driven directly, without the need for additional buffering circuitry. 1999 Oct 27 32 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 12 INTERRUPT SYSTEM The device has six interrupt sources, each of which can be enabled or disabled. When enabled each interrupt can be assigned one of two priority levels. There are four interrupts that are common to the 80C51, two of these are external interrupts (EX0 and EX1) and the other two are timer interrupts (ET0 and ET1). In addition to the conventional 80C51 interrupts, one application specific interrupt is incorporated internal to the device which has following functionality: * Display Busy interrupt (EBUSY). An interrupt is generated when the display enters either a Horizontal or Vertical Blanking Period. i.e. Indicates when the microcontroller can update the Display RAM without causing undesired effects on the screen. This interrupt can be configured in one of two modes using the Memory Mapped Register (MMR) Configuration (address 87FFH, bit TXT/V): - Text Display Busy. An interrupt is generated on each active horizontal display line when the Horizontal Blanking Period is entered - Vertical Display Busy. An interrupt is generated on each vertical display field when the Vertical Blanking Period is entered. 12.1 Interrupt enable structure SAA55xx If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined by the polling sequence as defined in Table 8. Table 8 Interrupt priority (within same level) PRIORITY WITHIN LEVEL highest - - - - lowest INTERRUPT VECTOR 0003H 000BH 0013H 001BH 002BH 0033H SOURCE EX0 ET0 EX1 ET1 ES2 EBUSY 12.3 Interrupt vector address The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine. The interrupt vector addresses for each source are shown in Table 8. 12.4 Level/edge interrupt Each of the individual interrupts can be enabled or disabled by setting or clearing the relevant bit in the Interrupt Enable Register (IE). All interrupt sources can also be globally disabled by clearing the EA bit (IE.7). 12.2 Interrupt enable priority The external interrupt can be programmed to be either level-activated or transition-activated by setting or clearing the IT0/IT1 bits in the Timer Control SFR (TCON). Table 9 ITx 0 1 External interrupt activation LEVEL active LOW - - INT0 = negative edge INTI = positive and negative edge The external interrupt INT1 differs from the standard 80C51 interrupt in that it is activated on both edges when in edge sensitive mode. This is to allow software pulse width measurement for handling remote control inputs. EDGE Each interrupt source can be assigned one of two priority levels. The interrupt priorities are defined by the Interrupt Priority Register (IP). A low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt. A high priority interrupt can not be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request with the highest priority level is serviced. 1999 Oct 27 33 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx handbook, full pagewidth EX0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 source enable SFR IE<0:6> global enable SFR IE.7 priority control SFR IP<0:6> highest priority level 1 highest priority level 0 ET0 EX1 ET1 ES2 EBUSY lowest priority level 1 lowest priority level 0 GSA033 interrupt source Fig.11 Interrupt structure. 1999 Oct 27 34 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 13 TIMER/COUNTER Two 16-bit timers/counters are incorporated Timer 0 and Timer 1. Both can be configured to operate as either timers or event counters. In Timer mode, the register is incremented on every machine cycle. It is therefore counting machine cycles. Since the machine cycle consists of twelve oscillator periods, the count rate is 112fosc = 1 MHz. In Counter mode, the register is incremented in response to a negative transition at its corresponding external pin T0 or T1. Since the pins T0 and T1 are sampled once per machine cycle, it takes two machine cycles to recognise a transition, this gives a maximum count rate of 1 f 24 osc = 0.5 MHz. There are six Special Function Registers used to control the timers/counters. These are: TCON, TMOD, TL0, TH0, TL1 and TH1. The timer/counter function is selected by control bits C/T in the Timer Mode SFR (TMOD). These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1 and M0) in TMOD. Detail of the modes of operation is given in "Handbook IC20, 80C51-Based 8-bit Microcontrollers". TL0 and TH0 are the actual Timer/Counter registers for Timer 0. TL0 is the low byte and TH0 is the high byte. TL1 and TH1 are the actual Timer/Counter registers for Timer 1. TL1 is the low byte and TH1 is the high byte. 14 WATCHDOG TIMER The Watchdog Timer is a counter that once in an overflow state forces the microcontroller into a reset condition. The purpose of the Watchdog Timer is to reset the microcontroller if it enters an erroneous processor state (possibly caused by electrical noise or RFI) within a reasonable period of time. When enabled, the Watchdog circuitry will generate a system reset if the user program fails to reload the Watchdog Timer within a specified length of time known as the Watchdog Interval (WI). The Watchdog Timer consists of an 8-bit counter with an 11-bit prescaler. The prescaler is fed with a signal whose frequency is 112fosc (1 MHz for 12 MHz oscillator). SAA55xx The 8-bit timer is incremented every `t' seconds where: 1 1 t = 12 x 2048 x -------- = 12 x 2048 x --------------------- = 2.048 ms 6 f osc 12 x 10 14.1 Watchdog Timer operation The Watchdog operation is activated when the WLE bit in the Power Control SFR (PCON) is set. The Watchdog can be disabled by software by loading the value 55H into the Watchdog Key SFR (WDTKEY). This must be performed before entering Idle or Power-down mode to prevent exiting the mode prematurely. Once activated the Watchdog Timer SFR (WDT) must be reloaded before the timer overflows. The WLE bit must be set to enable loading of the WDT SFR, once loaded the WLE bit is reset by hardware, this is to prevent erroneous software from loading the WDT SFR. The value loaded into the WDT defines the Watchdog Interval (WI). WI = ( 256 - WDT ) x t = ( 256 - WDT ) x 2.048 ms The range of intervals is from WDT = 00H which gives 524 ms to WDT = FFH which gives 2.048 ms. 15 PULSE WIDTH MODULATORS The device has eight 6-bit Pulse Width Modulated (PWM) outputs for analog control of e.g. volume, balance, bass, treble, brightness, contrast, hue and saturation. The PWM outputs generate pulse patterns with a repetition rate of 21.33 s, with the high time equal to the PWM SFR value multiplied by 0.33 s. The analog value is determined by the ratio of the high time to the repetition time, a DC voltage proportional to the PWM setting is obtained by means of an external integration network (low-pass filter). 15.1 PWM control The relevant PWM is enabled by setting the PWM enable bit PWxE in the PWMx Control Register (where x = 0 to 7). The high time is defined by the value PWxV<5:0>. 1999 Oct 27 35 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 15.2 Tuning Pulse Width Modulator (TPWM) SAA55xx The resolution of the DAC voltage with a nominal value is 3.3 256 13 mV. The external analog voltage has a lower value equivalent to VSSA and an upper value equivalent to VDDP - Vtn, where Vtn is the threshold voltage for an N type Metal Oxide Semiconductor transistor. The reason for this is that the input pins for the analog signals (P3.0 to P3.3) are 5 V tolerant for normal port operations, i.e. when not used as analog input. To protect the analog multiplexer and comparator circuitry from the 5 V, a series transistor is used to limit the voltage. This limiting introduces a voltage drop equivalent to Vtn (0.6 V) on the input voltage. Therefore, for an input voltage in the range VDDP to VDDP - Vtn the SAD returns the same comparison value. 15.3.3 SAD DC COMPARATOR MODE The device has a single 14-bit PWM that can be used for Voltage Synthesis Tuning. The method of operation is similar to the normal PWM except the repetition period is 42.66 s. 15.2.1 TPWM CONTROL Two SFRs are used to control the TPWM, they are TDACL and TDACH. The TPWM is enabled by setting the TPWE bit in the TDACH SFR. The most significant bits TD<13:7> alter the high period between 0 and 42.33 s. The 7 least significant bits TD<6:0> extend certain pulses by a further 0.33 s, e.g. if TD<6:0> = 01H then 1 in 128 periods will be extended by 0.33 s, if TD<6:0> = 02H then 2 in 128 periods will be extended. The TPWM will not start to output a new value until TDACH has been written to. Therefore, if the value is to be changed, TDACL should be written before TDACH. 15.3 Software ADC (SAD) Four successive approximation Analog-to-Digital Converters can be implemented in software by making use of the on-board 8-bit Digital-to-Analog Converter and Analog Comparator. 15.3.1 SAD CONTROL The SAD module incorporates a DC Comparator mode which is selected using the DC_COMP control bit in the SADB SFR. This mode enables the microcontroller to detect a threshold crossing at the input to the selected analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or P3.3/ADC3) of the Software ADC. A level sensitive interrupt is generated when the analog input voltage level at the pin falls below the analog output level of the SAD DAC. This mode is intended to provide the device with a wake-up mechanism from Power-down or Idle mode when a key-press on the front panel of the TV is detected. The following software sequence should be used when utilizing this mode for Power-down or Idle: 1. Disable INT1 using the IE SFR. 2. Set INT1 to level sensitive using the TCON SFR. 3. Set the DAC digital input level to the desired threshold level using SAD/SADB SFRs and select the required input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or P3.3/ADC3) using CH<1:0> in the SAD SFR. 4. Enter DC Compare mode by setting the DC_COMP enable bit in the SADB SFR. 5. Enable INT1 using the IE SFR. 6. Enter Power-down or Idle mode. Upon wake-up the SAD should be restored to its conventional operating mode by disabling the DC_COMP control bit. The control of the required analog input is done using the channel select bits CH<1:0> in the SAD SFR, this selects the required analog input to be passed to one of the inputs of the comparator. The second comparator input is generated by the DAC whose value is set by the bits SAD<7:0> in the SAD and SADB SFRs. A comparison between the two inputs is made when the start compare bit ST in the SAD SFR is set, this must be at least one instruction cycle after the SAD<7:0> value has been set. The result of the comparison is given on VHI one instruction cycle after the setting of ST. 15.3.2 SAD INPUT VOLTAGE The external analog voltage that is used for comparison with the internally generated DAC voltage does not have the same voltage range. The DAC has a lower reference level of VSSA and an upper reference level of VSSP. 1999 Oct 27 36 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx handbook, halfpage VDDP ADC0 ADC1 ADC2 ADC3 CH<1:0> VHI MUX 4:1 SAD<3:0> 8-BIT DAC SADB<3:0> MBK960 Fig.12 SAD block diagram. 1999 Oct 27 37 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 16 I2C-BUS SERIAL I/O The I2C-bus consists of a serial data (SDA) line and a serial clock (SCL) line. The definition of the I2C-bus protocol can be found in the document "The I2C-bus and how to use it (including specification)". This document may be ordered using the code 9398 393 40011. The device operates in four modes: * Master transmitter * Master receiver * Slave transmitter * Slave receiver. The microcontroller peripheral is controlled by the Serial Control SFR (S1CON) and its status is indicated by the Status SFR (S1STA). Information is transmitted/received to/from the I2C-bus using the Data SFR (S1DAT) and the Slave Address SFR (S1ADR) is used to configure the slave address of the peripheral. The byte level I2C-bus serial port is identical to the I2C-bus serial port on the P8xCE558, except for the clock rate selection bits CR<2:0> in S1CON. The operation of the subsystem is described in detail in the "P8xCE558 data sheet". 16.1 I2C-bus port selection 17.1 Memory structure SAA55xx The memory is partitioned into two distinct areas, the dedicated Auxiliary RAM area, and the Display RAM area. The Display RAM area when not being used for Data Capture or display, can be used as an extension to the auxiliary RAM area. 17.1.1 AUXILIARY RAM The Auxiliary RAM is not initialised at power-up. The contents of the Auxiliary RAM are maintained during Idle mode, but are lost if Power-down mode is entered. 17.1.2 DISPLAY RAM The Display RAM is initialised on power-up to a value of 20H throughout. The contents of the Display RAM are maintained when entering Idle mode. If Idle mode is exited using an interrupt then the contents are unchanged, if Idle mode is exited using a reset then the contents are initialised to 20H. 17.2 Memory mapping The dedicated Auxiliary RAM area occupies a maximum of 8 kbytes, with an address range from 0000H to 1FFFH. The Display RAM occupies a maximum of 10 kbytes with an address range from 2000H to 47FFH for TXT mode (see Fig.13). 17.3 Addressing memory Two I2C-bus ports are available SCL0/SDA0 and SCL1/SDA1. The selection of the port is done using TXT21.I2C PORT 0 and TXT21.I2C PORT 1. When the port is enabled, any information transmitted from the device goes onto the enabled port. Any information transmitted to the device can only be acted on if the port is enabled. If both ports are enabled then data transmitted from the device is seen on both ports, however data transmitted to the device on one port can not be seen on the other port. 17 MEMORY INTERFACE The memory interface controls access to the embedded Dynamic Random Access Memory (DRAM), refreshing of the DRAM and page clearing. The DRAM is shared between Data Capture, display and microcontroller sections. The Data Capture section uses the DRAM to store acquired information that has been requested. The display reads from the DRAM information and converts it into RGB values. The microcontroller uses the DRAM as embedded auxiliary RAM. The memory can be addressed by the microcontroller in two ways, either directly using a MOVX command, or via Special Function Registers depending on what address is required. The Display memory in the range 2000H to 47FFH can either be directly accessed using the MOVX, or via the Special Function Registers. 17.3.1 TXT DISPLAY MEMORY SFR ACCESS The Display memory when in TXT mode (see Fig.14) is configured as 40 columns wide by 25 rows and occupies 1K x 8 bits of memory. There can be a maximum of 10 display pages. Using TXT15.BLOCK<3:0>, the required display page can be selected to be written to. The row and column within that block is selected using TXT9.R<4:0> and TXT10.C<5:0>. The data at the selected position can be read or written using TXT11.D<7:0>. 1999 Oct 27 38 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) Whenever a read or write is performed on TXT11, the row values stored in TXT9 and column value stored in TXT10 are automatically incremented. For rows 0 to 24 the column value is incremented up to a maximum of 39, at which point it resets to `0' and increments the row counter value. When row 25 column 23 is reached the values of the row and column are both reset to zero. Writing values outside of the valid range for TXT9 or TXT10 will cause undetermined operation of the auto-incrementing function for accesses to TXT11. 17.3.2 TXT DISPLAY MEMORY MOVX ACCESS SAA55xx When this occurs, the space code (20H) is written into every location of rows 1 to 23 of the basic page memory, the appropriate packet 27 row of the extension packet memory and the row where teletext packet 24 is written. This last row is either row 24 of the basic page memory, if the TXT0.X24 POSN bit is set, or row 0 of the extension packet memory, if the bit is not set. Page clearing takes place before the end of the TV line in which the header arrived which initiated the page clear. This means that the 1 field gap between the page header and the rest of the page which is necessary for many teletext decoders is not required. 17.4.2 SOFTWARE PAGE CLEAR It is important for the generation of OSD displays, that use this mode of access, to understand the mapping of the MOVX address onto the display row and column value. This mapping of row and column onto address is shown in Table 10. The values shown are added onto a base address for the required memory block (see Fig.13) to give a 16-bit address. 17.4 Page clearing The software can also initiate a page clear, by setting the TXT9.CLEAR MEMORY bit. When it does so, every location in the memory block pointed to by TXT15.BLOCK<3:0> is cleared to a space code (20H). The CLEAR MEMORY bit is not latched so the software does not have to reset it after it has been set. Only one page can be cleared in a TV line so if the software requests a page clear it will be carried out on the next TV line on which the Data Capture hardware does not force the page to be cleared. A flag, TXT13.PAGE CLEARING, is provided to indicate that a software requested page clear is being carried out. The flag is set when a logic 1 is written into the TXT9.CLEAR MEMORY bit and is reset when the page clear has been completed. If TXT0.INV ON bit = 1 and a page clear is initiated on Block 8 all locations are cleared to 00H. Page clearing is performed on request from either the Data Capture block, or the microcontroller under the control of the embedded software. At power-on and reset the whole of the page memory is cleared. The TXT13.PAGE CLEARING bit will be set while this takes place. 17.4.1 DATA CAPTURE PAGE CLEAR When a page header is acquired for the first time after a new page request or a page header is acquired with the erase (C4) bit set the page memory is `cleared' to spaces before the rest of the page arrives. Table 10 Column and row to MOVX address (lower 10 bits of address) ROW Row 0 Row 1 : : Row 23 Row 24 Row 25 COL. 0 000H 020H : : 2E0H 300H 320H ..... ..... ..... : : ..... ..... ..... COL. 23 017H 037H : : 3F7H 317H 337H ..... ..... ..... : : ..... ..... ..... COL. 31 COL. 32 01FH 03FH : : 2FFH 31FH ..... 3F8H 3F0H : : 340H 338H ..... ..... ..... ..... : : ..... ..... ..... COL. 39 3FFH 3F7H : : 347H 33FH : 1999 Oct 27 39 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx lower 32 kbytes handbook, halfpage 7FFFH TXT BLOCK 8 TXT BLOCK 7 TXT BLOCK 6 TXT BLOCK 5 TXT BLOCK 4 TXT BLOCK 3 TXT BLOCK 2 TXT BLOCK 1 TXT BLOCK 9 TXT BLOCK 0 4400H 4000H 3C00H 3800H 3400H 3000H 2C00H 2800H 2400H 2000H AUXILIARY 0000H GSA034 Fig.13 DRAM memory mapping. 1999 Oct 27 40 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx handbook, full pagewidth 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 control data 10 C Column 20 30 39 9 10 23 non-displayable data (byte 10 reserved) active position TXT9.R<4:0> = 01H, TXT10.C<5:0> = 0AH, TXT11 = 43H MBK962 Fig.14 TXT memory map. 1999 Oct 27 41 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 18 DATA CAPTURE The Data Capture section takes in the analog Composite Video and Blanking Signal (CVBS), and from this extracts the required data, which is then decoded and stored in memory. The extraction of the data is performed in the digital domain. The first stage is to convert the analog CVBS signal into a digital form. This is done using an ADC sampling at 12 MHz. The data and clock recovery is then performed by a Multi-Rate Video Input Processor (MulVIP). From the recovered data and clock the following data types are extracted: WST Teletext (625/525), VPS and WSS. The extracted data is stored in either memory (DRAM) via the Memory interface or in SFR locations. 18.1 Data Capture features SAA55xx * Data Capture for Wide Screen Signalling (WSS) bit decoding * Automatic selection between 525 WST/625 WST * Automatic selection between 625 WST/VPS on line 16 of Vertical Blanking Interval (VBI) * Real-time capture and decoding for WST Teletext in hardware, to enable optimized microprocessor throughput * Up to 10 pages stored on-chip * Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) and Subtitle Page Table (SPT) * Automatic detection of FASTEXT transmission * Real-time packet 26 engine in hardware for processing accented, G2 and G3 characters * Signal quality detector for WST/VPS data types * Comprehensive Teletext language coverage * Full Field and Vertical Blanking Interval (VBI) data capture of WST data. * Two CVBS inputs * Video Signal Quality detector * Data Capture for 625-line WST * Data Capture for 525-line WST * Data Capture for VPS data (Programme Delivery Control (PDC) system A) handbook, full pagewidth CVBS0 CVBS1 CVBS SWITCH CVBS ADC data<7:0> DATA SLICER AND CLOCK RECOVERY TTC TTD SYNC SEPARATOR VCS ACQUISITION TIMING SYNC_FILTER ACQUISITION FOR WST/VPS/WSS output data to memory interface and SFRs GSA032 Fig.15 Data capture block diagram. 1999 Oct 27 42 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 18.1.1 CVBS SWITCH SAA55xx 18.1.6.1 Making a page request The CVBS switch is used to select the required analog input depending on the value of TXT8.CVBS1/CVBS0. 18.1.2 ANALOG-TO-DIGITAL CONVERTER The output of the CVBS switch is passed to a differential-to-single-ended converter, although in this device it is used in single-ended configuration with a reference. The analog output of the differential amplifier is converted into a digital representation by a full flash ADC with a sampling rate of 12 MHz. 18.1.3 MULTI-RATE VIDEO INPUT PROCESSOR A page is requested by writing a series of bytes into the TXT3.PRD<4:0> SFR which corresponds to the number of the page required. The bytes written into TXT3 are stored in a RAM with an auto-incrementing address. The start address for the RAM is set using the TXT2.SC<2:0> to define which part of the page request is being written, and TXT2.REQ<3:0> is used to define which of the 10 page requests is being modified. If TXT2.REQ<3:0> is greater than 09H, then data being written to TXT3 is ignored. Table 12 shows the contents of the page request RAM. Up to 10 pages of teletext can be acquired on the 10 page device, when TXT1.EXT PKT OFF is set to logic 1, and up to 9 pages can be acquired when this bit is set to logic 0. For a 20 page device the 10 page acquisition channels are banked, the bank being selected using TXT2.ACQ BANK. If the `DO CARE' bit for part of the page number is set to logic 0 then that part of the page number is ignored when the teletext decoder is deciding whether a page being received off air should be stored or not. For example, if the `DO CARE' bits for the four subcode digits are all set to logic 0 then every subcode version of the page will be captured. Table 12 The contents of the Page request RAM START COLUMN 0 1 PRD4 DO CARE Magazine DO CARE Page Tens PRD3 PRD2 PRD1 PRD0 HOLD MAG2 MAG1 MAG0 PT3 PT2 PU2 X HU2 PT1 PU1 HT1 HU1 PT0 PU0 HT0 HU0 The multi-rate video input processor is a Digital Signal Processor designed to extract the data and recover the clock from a digitised CVBS signal. 18.1.4 DATA STANDARDS The data and clock standards that can be recovered are shown in Table 11. Table 11 Data slicing standards DATA STANDARD 625 WST 525 WST VPS WSS 18.1.5 DATA CAPTURE TIMING CLOCK RATE (MHz) 6.9375 5.7272 5.0 5.0 The Data Capture timing section uses the synchronisation information extracted from the CVBS signal to generate the required horizontal and vertical reference timings. The timing section automatically recognises and selects the appropriate timings for either 625 (50 Hz) synchronisation or 525 (60 Hz) synchronisation. A flag TXT12.VIDEO SIGNAL QUALITY is set when the timing section is locked correctly to the incoming CVBS signal. When TXT12.VIDEO SIGNAL QUALITY is set another flag TXT12.525/625 SYNC can be used to identify the standard. 18.1.6 ACQUISITION 2 3 4 DO CARE PU3 Page Units DO CARE Hour Tens DO CARE Hours Units DO CARE Minutes Tens DO CARE Minutes Units X X HU3 5 X MT2 MT1 MT0 6 MU3 MU2 MU1 MU0 The acquisition sections extracts the relevant information from the serial stream of data from the MulVIP and stores it in memory. 7 X X E1 E0 1999 Oct 27 43 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) When the HOLD bit is set to a logic 0 the teletext decoder will not recognise any page as having the correct page number and no pages will be captured. In addition to providing the user requested hold function this bit should be used to prevent the inadvertent capture of an unwanted page when a new page request is being made. For example, if the previous page request was for page 100 and this was being changed to page 234, it would be possible to capture page 200 if this arrived after only the requested magazine number had been changed. The E1 and E0 bits control the error checking which should be carried out on packets 1 to 23 when the page being requested is captured. This is described in more detail in Section 18.1.6.3. For a multi-page device, each packet can only be written into one place in the teletext RAM so if a page matches more than one of the page requests the data is written into the area of memory corresponding to the lowest numbered matching page request. At power-up each page request defaults to any page, hold on and error check Mode 0. SAA55xx When a requested page header is acquired for the first time, rows 1 to 23 of the relevant memory block are cleared to space, i.e. have 20H written into every column, before the rest of the page arrives. Row 24 is also cleared if the TXT0.X24 POSN bit is set. If the TXT1.EXT PKT OFF bit is set the extension packets corresponding to the page are also cleared. The last 8 characters of the page header are used to provide a time display and are always extracted from every valid page header as it arrives and written into the display block. The TXT0.DISABLE HEADER ROLL bit prevents any data being written into row 0 of the page memory except when a page is acquired off air i.e. rolling headers and time are not written into the memory. The TXT1.ACQ OFF bit prevents any data being written into the memory by the teletext acquisition section. When a parallel magazine mode transmission is being received only headers in the magazine of the page requested are considered valid for the purposes of rolling headers and time. Only one magazine is used even if don't care magazine is requested. When a serial magazine mode transmission is being received all page headers are considered to be valid. 18.1.6.2 Rolling headers and time When a new page has been requested it is conventional for the decoder to turn the header row of the display green and to display each page header as it arrives until the correct page has been found. When a page request is changed (i.e. when the TXT3 SFR is written to) a flag (PBLF) is written into bit 5, column 9, row 25 of the corresponding block of the page memory. The state of the flag for each block is updated every TV line, if it is set for the current display block, the acquisition section writes all valid page headers which arrive into the display block and automatically writes an alphanumeric green character into column 7 of row 0 of the display block every TV line. 18.1.6.3 Error checking Before teletext packets are written into the page memory they are error checked. The error checking carried out depends on the packet number, the byte number, the error check mode bits in the page request data and the TXT1.8-BIT bit. If an uncorrectable error occurs in one of the Hamming checked addressing and control bytes in the page header or in the Hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory is set, to act as an error flag to the software. If uncorrectable errors are detected in any other Hamming checked data the byte is not written into the memory. 1999 Oct 27 44 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx Packet X/0 handbook, full pagewidth '8-bit' bit = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet X/1-23 '8-bit' bit = 0, error check mode = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 0, error check mode = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 0, error check mode = 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 0, error check mode = 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet X/24 '8-bit' bit = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 '8-bit' bit = 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet X/27/0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet 8/30/0,1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Packet 8/30/2,3,4-15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 MGK465 8-bit data odd parity checked 8/4 Hamming checked Fig.16 Error checking. 1999 Oct 27 45 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx handbook, full pagewidth Basic Page Blocks (0 to 8/9) 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 Control Data 9 10(3) 6 7 8 Packet X/0 Packet X/1 Packet X/2 Packet X/3 Packet X/4 Packet X/5 Packet X/6 Packet X/7 Packet X/8 Packet X/9 Packet X/10 Packet X/11 Packet X/12 Packet X/13 Packet X/14 Packet X/15 Packet X/16 Packet X/17 Packet X/18 Packet X/19 Packet X/20 Packet X/21 Packet X/22 Packet X/23 Packet X/24(1) VPS Data(2) 23 GSA003 39 OSD only (1) If `X24 POSN' bit = 1. (2) VPS data block 9, unused in blocks 0 to 8. (3) Byte 10 reserved. Fig.17 Packet storage locations. 1999 Oct 27 46 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 18.1.6.4 Teletext memory organisation SAA55xx Packet 0, the page header, is split into two parts when it is written into the text memory. The first 8 bytes of the header contain control and addressing information. They are Hamming decoded and written into columns 0 to 7 of row 25. Row 25 also contains the magazine number of the acquired page and the PLBF flag but the last 14 bytes are unused and may be used by the software, if necessary. The teletext memory is divided into 2 banks of 10 blocks. Normally, when the TXT1.EXT PKT OFF bit is logic 0, each of blocks 0 to 8 contains a teletext page arranged in the same way as the basic page memory of the page device and block 9 contains extension packets. When the TXT1.EXT PKT OFF bit is logic 1, no extension packets are captured and block 9 of the memory is used to store another page. The number of the memory block into which a page is written corresponds to the page request number which resulted in the capture of the page. Extension Packet Block (9) handbook, full pagewidth Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 Packet X/24 for page in block 0(1) Packet X/27/0 for page in block 0 Packet 8/30/0.1 Packet 8/30/2.3 Packet X/24 for page in block 1(1) Packet X/27/0 for page in block 1 Packet X/24 for page in block 2(1) Packet X/27/0 for page in block 2 Packet X/24 for page in block 3(1) Packet X/27/0 for page in block 3 Packet X/24 for page in block 4(1) Packet X/27/0 for page in block 4 Packet X/24 for page in block 5(1) Packet X/27/0 for page in block 5 Packet X/24 for page in block 6(1) Packet X/27/0 for page in block 6 Packet X/24 for page in block 7(1) Packet X/27/0 for page in block 7 Packet X/24 for page in block 8(1) Packet X/27/0 for page in block 8 Packet 8/30/4-15 VPS Data 9 10(2) 23 GSA002 (1) If `X24 POSN' bit = 0. (2) Byte 10 reserved. Fig.18 Extension packet storage locations. 1999 Oct 27 47 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 18.1.6.5 Row 25 data contents SAA55xx The magazine serial (C11) bit indicates whether the transmission is a serial or a parallel magazine transmission. This affects the way the acquisition section operates and is dealt with automatically. The newsflash (C5), subtitle (C6), suppress header (C7), inhibit display (C10) and language control (C12 to 14) bits are dealt with automatically by the display section. The update (C8) bit has no effect on the hardware. The remaining 32 bytes of the page header are parity checked and written into columns 8 to 39 of row 0. Bytes which pass the parity check have the MSB set to a logic 0 and are written into page memory. Bytes with parity errors are not written into the memory. The Hamming error flags are set if the on-board 8/4 Hamming checker detects that there has been an uncorrectable (2-bit) error in the associated byte. It is possible for the page to still be acquired if some of the page address information contains uncorrectable errors if that part of the page request was a `don't care'. There is no error flag for the magazine number as an uncorrectable error in this information prevents the page being acquired. The interrupt sequence (C9) bit is automatically dealt with by the acquisition section so that rolling headers do not contain a discontinuity in the page number sequence. Table 13 The data in row 25 of the basic page memory COL 0 1 2 3 4 5 6 7 8 9 10 to 23 BIT 7 0 0 0 0 0 0 0 0 0 0 - BIT 6 0 0 0 0 0 0 0 0 0 0 - BIT 5 0 0 0 0 0 0 0 0 0 PBLF - BIT 4 Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error Hamming error FOUND 0 unused BIT 3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0 - BIT 2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0 - BIT 1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0 - BIT 0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0 - 1999 Oct 27 48 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 18.1.6.6 Inventory page SAA55xx The bit for a particular page in the TPT is set when a page header is received for that page. The bit in the SPT is set when a page header for the page is received which has the `subtitle' page header control bit (C6) set. The bit for a particular page in the TPT is set when a page header is received for that page. The bit in the SPT is set when a page header for the page is received which has the `subtitle' page header control bit (C6) set. If the TXT0.INV ON bit is a logic 1, memory block 8 is used as an inventory page.The inventory page consists of two tables: the Transmitted Page Table (TPT) and the Subtitle Page Table (SPT). In each table, every possible combination of the page tens and units digit, 00H to FFH, is represented by a byte. Each bit of these bytes corresponds to a magazine number so each page number, from 100H to 8FFH, is represented by a bit in the table. Bytes in the table handbook, full pagewidth column 0 8 16 24 32 39 row n n+1 n+6 n+7 bits in each byte xe0 xe1 xe2 xe3 xe4 xe5 xe6 xe7 xe8 xe9 xea xeb xec xed xee xfef xf0 xf1 xf2 xf3 xf4 xf5 xf6 xf7 xf8 xf9 xfa xfb xfc xfd xfe xff bit 7 7xx 6xx 5xx 4xx 3xx 2xx 1xx 0 8xx xc0 xc1 xc2 xc3 xc4 xc5 xc6 xc7 xc8 xc9 xca xcb xcc xcd xce xcf xd0 xd1 xd2 xd3 xd4 xd5 xd6 xd7 xd8 xd9 xda xdb xdc xdd xde xdf x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x2a x2b x2c x2d x2e x2f x30 x31 x32 x33 x34 x35 x36 x37 x38 x39 x3a x3b x3c x3d x3e x3f x00 x01 x02 x03 x04 x05 x06 x07 x08 x09 x0a x0b x0c x0d x0e x0f x10 x11 x12 x13 x14 x15 x16 x17 x18 x19 x1a x1b x1c x1d x1e x1f MGD160 Fig.19 Transmitted/subtitle page organisation. 1999 Oct 27 49 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx 0 handbook, full pagewidth 39 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 Transmitted Pages Table Subtitle Pages Table Unused Unused Unused Unused Unused Unused Unused Unused Unused 23 MGD165 Fig.20 Inventory page organisation. 1999 Oct 27 50 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 18.1.6.7 Packet 26 processing 18.3 VPS acquisition SAA55xx One of the uses of packet 26 is to transmit characters which are not in the basic teletext character set. The family automatically decodes packet 26 data and, if a character corresponding to that being transmitted is available in the character set, automatically writes the appropriate character code into the correct location in the teletext memory. This is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and so is often referred to as level 1.5. By convention, the packets 26 for a page are transmitted before the normal packets. To prevent the default character data overwriting the packet 26 data the device incorporates a mechanism which prevents packet 26 data from being overwritten. The mechanism is disabled when the Spanish national option is detected as the Spanish transmission system sends even parity (i.e. incorrect) characters in the basic page locations corresponding to the characters sent via packet 26 and these will not overwrite the packet 26 characters anyway. The special treatment of Spanish national option is prevented if TXT12.ROM VER3 is logic 0 or if the TXT8.DISABLE SPANISH is set. Packet 26 data is processed regardless of the TXT1.EXT PKT OFF bit, but setting theTXT1.X26 OFF disables packet 26 processing. The TXT8.PKT26 RECEIVED bit is set by the hardware whenever a character is written into the page memory by the packet 26 decoding hardware. The flag can be reset by writing a logic 0 into the SFR bit. 18.1.7 WST ACQUISITION When the TXT0.VPS ON bit is set, any VPS data present on line 16, field 0 of the CVBS signal at the input of the teletext decoder is error checked and stored in row 25, block 9 of the basic page memory. The device automatically detects whether teletext or VPS is being transmitted on this line and decodes the data appropriately. Each VPS byte in the memory consists of 4 biphase decoded data bits (bits 0 to 3), a biphase error flag (bit 4) and three logic 0s (bits 5 to 7). The TXT13.VPS RECEIVED bit is set by the hardware whenever VPS data is acquired. Full details of the VPS system can be found in the "Specification of the Domestic Video Programme Delivery Control System (PDC); EBU Tech. 3262-E". 18.4 WSS acquisition The Wide Screen Signalling data transmitted on line 23 gives information on the aspect ratio and display position of the transmitted picture, the position of subtitles and on the camera/film mode. Some additional bits are reserved for future use. A total of 14 data bits are transmitted. All of the available data bits transmitted by the Wide Screen Signalling signal are captured and stored in SFRs WSS1, WSS2 and WSS3. The bits are stored as groups of related bits, and an error flag is provided for each group to indicate when a transmission error has been detected in one or more of the bits in the group. Wide screen signalling data is only acquired when the TXT8.WSS ON bit is set. The TXT8.WSS RECEIVED bit is set by the hardware whenever wide screen signalling data is acquired. The flag can be reset by writing a logic 0 into the SFR bit. The family is capable of acquiring Level 1.5 625-line and 525-line World System Teletext. 18.2 Broadcast service data detection When a packet 8/30 is detected, or a packet 4/30 when the device is receiving a 525 line transmission, the TXT13. PKT 8/30 flag is set. The flag can be reset by writing a 0 into the SFR bit. handbook, full pagewidth column 0 row 25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 teletext page header data VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 VPS byte 15 VPS byte 4 VPS byte 5 MBK964 Fig.21 VPS data storage. 1999 Oct 27 51 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 19 DISPLAY The display section is based on the requirements for a Level 1.5 WST Teletext. There are some enhancements for use with locally generated OSDs. The display section reads the contents of the Display memory and interprets the control/character codes. From this information and other global settings, the display produces the required RGB signals and Video/Data (Fast Blanking) signal for a TV signal processing device. The display is synchronised to the TV signal processing device by way of horizontal and vertical sync signals provided by external circuits (Slave Sync mode). From these signals all display timings are derived. 19.1 Display features * Level 1.5 WST features SAA55xx * Single/Double/Quadruple Width and Height for characters * Variable flash rate controlled by software * Fixed character matrix (H x V) 12 x 10 * Soft colours using Colour Look Up Table (CLUT) with 4096 colour palette * Fringing (Shadow) selectable from N-S-E-W direction * Fringe colour selectable * Meshing of defined area * Contrast reduction of defined area * Cursor * 1 WST Character set (G0/G2) in single device (e.g. Latin or Cyrillic or Greek or Arabic) * G1 Mosaic graphics, Limited G3 Line drawing characters. * Teletext and Enhanced On-Screen Display (OSD) modes handbook, full pagewidth CLK VSYNC HSYNC DISPLAY TIMING address MICROPROCESSOR INTERFACE data FUNCTION REGISTERS address to memory interface from memory interface address data data DISPLAY DATA ADDRESSING ATTRIBUTE HANDLING address data control PARALLEL/SERIAL CONVERTER AND FRINGING DATA BUFFER CHARACTER ROM AND DRCs data CHARACTER FONT ADDRESSING CLUT RAM address DAC DAC DAC MBK965 R G B FB Fig.22 Display block diagram. 1999 Oct 27 52 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 19.2 Display mode SAA55xx Any two consecutive combination of `double width' or `double size' (0EH/BEH/0FH/BFH) activates quadruple width characters, provided quadruple width characters are enabled by TXT4.QUAD WIDTH ENABLE. Three vertical sizes are available normal (x1), double (x2), quadruple (x4). The control characters `normal size' (0CH/BCH) enable normal size, the `double height' or `double size' (0DH/BDH/0FH/BFH) enable double height characters. Quadruple height characters are achieved by using double height characters and setting the global attributes TXT7.DOUBLE HEIGHT (expand) and TXT7.BOTTOM/TOP. If double height characters are used in Teletext mode, single height characters in the lower row of the double height character are automatically disabled. 19.3.4 COLOURS The display is configured as WST with additional serial and global attributes. The display is configured as a fixed 25 rows with 40 characters per row. 19.3 19.3.1 Display feature descriptions FLASH Flashing causes the foreground colour pixel to be displayed as the background pixels.The flash frequency is controlled by software setting and resetting the MMR Status (see Table 24) at the appropriate interval. This attribute is set by the control character `flash' (08H) (see Fig.26) and remains valid until the end of the row or until reset by the control character `steady' (09H). 19.3.2 BOXES Two types of boxes exist, the Teletext box and the OSD box. The Teletext box is activated by the `start box' control character (0BH), two start box characters are required to begin a Teletext box, with the box starting between the two characters. The box ends at the end of the line or after a `end box' control character. OSD boxes are started using size implying OSD control characters (BCH, BDH, BEH and BFH). The box starts after the control character (`set after') and ends either at the end of the row or at the next size implying OSD character (`set at'). The attributes flash, Teletext box, conceal, separate graphics, twist and hold graphics are all reset at the start of an OSD box, as they are at the start of the row. OSD boxes are only valid in TV mode which is defined by TXT5 = 03H and TXT6 = 03H. 19.3.3 SIZE 19.3.4.1 Colour Look Up Table (CLUT) A CLUT with 16 colour entries is provided. The colours are programmable out of a palette of 4096 (4 bits per R, G and B). The CLUT is defined by writing data to a RAM that resides in the MOVX address space of the 80C51. Table 14 CLUT colour values RED<3:0> (B11 TO B8) 0000 0000 ... 1111 1111 GRN<3:0> (B7 TO B4) 0000 0000 ... 1111 1111 BLUE<3:0> (B3 TO B0) 0000 1111 ... 0000 1111 COLOUR ENTRY 0 1 ... 14 15 The size of the characters can be modified in both the horizontal and vertical directions. Three horizontal sizes are available normal (x1), double (x2), quadruple (x4). The control characters `normal size' (0CH/BCH) enables normal size, the `double width' or `double size' (0EH/BEH/0FH/BFH) enables double width characters. 19.3.5 FOREGROUND COLOUR The foreground colour is selected via a control character (see Fig.26). The colour control characters take effect at the start of the next character (set-after) and remain valid until the end of the row, or until modified by a control character. Only 8 foreground colours are available. The TEXT foreground control characters map to the CLUT entries as shown in Table 15. 1999 Oct 27 53 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) Table 15 Foreground CLUT mapping CONTROL CODE 00H 01H 02H 03H 04H 05H 06H 07H 19.3.6 DEFINED COLOUR black red green yellow blue magenta cyan white CLUT ENTRY 0 1 2 3 4 5 6 7 19.3.7 FRINGING SAA55xx The display of fringing is controlled by the TXT4.SHADOW bit. When set all the alphanumeric characters being displayed are shadowed, graphics characters are not shadowed. 19.3.8 MESHING The attribute effects the background colour being displayed. Alternate pixels are displayed as the background colour or video. The structure is offset by 1 pixel from scan line to scan line, thus achieving a checker board display of the background colour and video. TXT: There are two meshing attributes one that only affects black background colours TXT4.B MESH ENABLE and a second that only affects backgrounds other than black TXT4.C MESH ENABLE. A black background is defined as CLUT entry 8, a non-black background is defined as CLUT entry 9 to 15. 19.3.9 CURSOR BACKGROUND COLOUR The control character new background (1DH) is used to change the background colour to the current foreground colour. The selection is immediate (set at) and remains valid until the end of the row or until otherwise modified. The TEXT background control characters map to the CLUT entries as shown in Table 16. Table 16 Background CLUT mapping CONTROL CODE 00H + 1DH 01H + 1DH 02H + 1DH 03H + 1DH 04H + 1DH 05H + 1DH 06H + 1DH 07H + 1DH DEFINED COLOUR black red green yellow blue magenta cyan white CLUT ENTRY 8 9 10 11 12 13 14 15 The cursor operates by reversing the background and foreground colours in the character position pointed to by the active cursor position. The cursor is enabled using TXT7.CURSOR ON. When active, the row the cursor appears on is defined by TXT9.R<4:0> and the column is defined by TXT10.C<5:0>. The position of the cursor can be fixed using TXT9.CURSOR FREEZE. The valid range for row positioning is 0 to 24. The valid range for column is 0 to 39. 1999 Oct 27 54 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx handbook, full pagewidth MBK972 Fig.23 South and south-west fringing. handbook, full pagewidth MBK973 Fig.24 Meshing and meshing/fringing (south + west). handbook, full pagewidth AB C D E F MBK971 Fig.25 Cursor display. 1999 Oct 27 55 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 19.4 Character and attribute coding SAA55xx The character coding is in a serial format, with only one attribute being changed at any single location. The serial attributes take effect either at the position of the attribute (set at), or at the following location (set after). The attribute remains effective until either modified by new serial attributes or until the end of the row. The default settings at the start of a row is: * Foreground colour white (CLUT address 7) * Background colour black (CLUT address 8) * Horizontal size x1, vertical size x1 (normal size) * Alphanumeric on * Contiguous Mosaic Graphics * Release Mosaics * Flash off * Box off * Conceal off * Twist off. The attributes have individual codes which are defined in the basic character table (see Fig.26). 1999 Oct 27 56 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Oct 27 57 Philips Semiconductors Standard TV microcontrollers with On-Screen Display (OSD) E/W = 0 B I T S b7 b6 b5 b4 b3 b2 b1 b0 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green 0 0 0 1 2 0 0 1 0 2a 3 0 0 1 1 3a 4 nat opt 0 1 0 0 5 0 1 0 1 6 nat opt 0 1 1 0 6a 7 0 1 1 1 7a 8 1 0 0 0 8a 9 1 0 0 1 9a A 1 0 1 0 B background black back ground red background green background yellow background blue background magenta background cyan background white 1 0 1 1 C 1 1 0 0 D 1 1 0 1 E 1 1 1 0 F 1 1 1 1 D 1 1 0 1 E/W = 1 1 1 1 0 E F 1 1 1 1 alpha black alpha red OSD OSD OSD OSD 0 0 0 1 1 OSD OSD OSD OSD 0 0 1 0 2 alpha green alpha yellow OSD OSD OSD OSD 0 0 1 1 3 graphics yellow nat opt OSD OSD OSD OSD 0 1 0 0 4 alpha blue alpha magenta graphics blue graphics magenta nat opt OSD OSD OSD OSD 0 1 0 1 5 OSD OSD OSD OSD 0 1 1 0 6 alpha cyan alpha white graphics cyan graphics white conceal display OSD OSD OSD OSD 0 1 1 1 7 OSD OSD OSD OSD 1 0 0 0 8 flash OSD OSD OSD OSD 1 0 0 1 9 steady contiguous graphics separated graphics OSD OSD OSD OSD 1 0 1 0 A end box OSD OSD OSD OSD 1 0 1 1 B start box twist nat opt nat opt OSD OSD OSD OSD normal size OSD double height OSD double width OSD double size OSD 1 1 0 0 C normal height double height black back ground new back ground hold graphics release graphics nat opt nat opt OSD OSD OSD OSD 1 1 0 1 D nat opt nat opt nat opt nat opt OSD OSD OSD OSD 1 1 1 0 E double width double size Preliminary specification OSD OSD OSD OSD 1 1 1 1 F nat opt handbook, full pagewidth OSD OSD OSD OSD SAA55xx MBK974 nat opt OSD character dependent on the language of page, refer to National Option characters customer definable On-Screen Display character Fig.26 TXT basic character set (Pan-European). Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 19.5 Screen and global controls SAA55xx The use of teletext boxes for OSD messages has been superseded in this device by the OSD box concept, but these bits remain to allow teletext boxes to be used, if required. 19.6 Screen colour A number of attributes are available that affect the whole display region, and cannot be applied selectively to regions of the display. 19.5.1 DISPLAY MODES The display mode is controlled by the bits in the TXT5 and TXT6. There are three control functions: Text on, Background on and Picture on. Separate sets of bits are used inside and outside teletext boxes so that different display modes can be invoked. TXT6 is used if the newsflash (C5) or subtitle (C6) bits in row 25 of the basic page memory are set, otherwise TXT5 is used. This allows the software to set up the type of display required on newsflash and subtitle pages (e.g. text inside boxes, TV picture outside) this will be invoked without any further software intervention when such a page is acquired. When teletext box control characters are present in the display page memory, the appropriate box control bit must be set, TXT7.BOX ON 0, TXT7.BOX ON 1 - 23 or TXT7.BOX ON 24. This allows the display mode to be different inside the Teletext box compared to outside. These bits are present to allow boxes in certain areas of the screen to be disabled. Table 17 TXT display control bits PICTURE ON 0 0 0 1 1 1 TEXT ON 0 1 1 0 1 1 Screen colour is displayed from 10.5 to 62.5 ms after the active edge of the HSYNC input and on TV lines 23 to 310 inclusive, for a 625-line display, and lines 17 to 260 inclusive for a 525-line display. The register bits TXT17.SCREEN COL<2:0> can be used to define a colour to be displayed in place of TV picture and the black background colour. If the bits are all set to zero, the screen colour is defined as `transparent' and TV picture and background colour are displayed as normal. Otherwise the bits define CLUT entries 9 to 15. 19.7 Text display control The display is organised as a fixed size of 25 rows (0 to 24) of 40 columns (0 to 39), This is the standard size for teletext transmissions. The control data in row 25 is not displayed but is used to configure the display page correctly. BACKGROUND ON X 0 1 X 0 1 EFFECT Text mode, black screen Text mode, background always black Text mode Video mode Mixed text and TV mode Text mode, TV picture outside text area 1999 Oct 27 58 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx handbook, full pagewidth 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 control data 9 10 23 39 non-displayable data byte 10 reserved MBK968 Fig.27 TXT text area. 1999 Oct 27 59 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 19.8 Display positioning SAA55xx The screen colour extends over a large vertical and horizontal range so that no offset is needed. The text area is offset in both directions relative to the vertical and horizontal sync pulses. The display consists of the screen colour covering the whole screen and the text area that is placed within the visible screen area. handbook, full pagewidth horizontal sync screen colour offset = 8 s 6 lines offset text vertical offset SCREEN COLOUR AREA horizontal sync delay TEXT AREA vertical sync 0.25 character offset text area start text area end 56 s MGL150 Fig.28 Display area positioning. 1999 Oct 27 60 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 19.8.1 SCREEN COLOUR DISPLAY AREA SAA55xx Note that the Text Position Vertical Register should not be set to 00H as the Display Busy interrupt is not generated in these circumstances. 19.9 Character set This area is covered by the screen colour. The screen colour display area starts with a fixed offset of 8 s from the leading edge of the horizontal sync pulse in the horizontal direction. A vertical offset is not necessary. Table 18 Screen colour display area VECTOR Horizontal Vertical DESCRIPTION Start at 8 s after leading edge of horizontal sync for 56 s. Line 9, field 1 (321, field 2) to leading edge of vertical sync (line numbering using 625 standard). TEXT DISPLAY AREA A set can consist of alphanumeric characters as required by WST Teletext or customer definable OSD characters. Two character sets can be displayed at once. These are the basic G0 set or the alternate G2 set (Twist Set). The basic set is selected using TXT18.BS<1:0>. The alternate/twist character set is defined by TXT19.TS<1:0>. Since the alternate character set is an option it can be enabled or disabled using TXT19.TEN, and the language code that is defined for the alternate set is defined by TXT19.TC<2:0>. 19.10 Display synchronization The horizontal and vertical synchronizing signals from the TV deflection are used as inputs. Both signals can be inverted before being delivered to the Phase Selector section. SFRs bits TXT1.HPOLARITY and TXT1.VPOLARITY control the polarity. A line locked 12 MHz clock is derived from the 12 MHz free running oscillator by the Phase Selector. This line locked clock is used to clock the whole of the Display block. The horizontal and vertical sync signals are synchronized with the 12 MHz clock before being used in the Display section. 19.11 Video/data switch (fast blanking) polarity The polarity of the Video/data (fast blanking) signal can be inverted. The polarity is set with the VDSPOL bit in the MMR RGB Brightness. Table 20 Fast blanking signal polarity VDSPOL 0 0 1 1 VDS 1 0 0 1 CONDITION RGB display Video display RGB display Video display 19.8.2 The text area can be defined to start with an offset in both the horizontal and vertical direction. Table 19 Text display area VECTOR Horizontal DESCRIPTION Up to 40 full sized characters per row. Start position setting from 8 to 64 characters from the leading edge of horizontal sync. Fine adjustment in quarter characters. 256 lines (nominal 41 to 297). Start position setting from leading edge of vertical sync, legal values are 4 to 64 lines. (line numbering using 625 standard). Vertical The horizontal offset is set in the MMR Text Area Start. The offset is done in full width characters using TAS<5:0> and quarter characters using HOP<1:0> for fine setting. The values 00H to 08H for TAS<5:0> will result in a corrupted display. The width of the text area is defined in the MMR Text Area End by setting the end character value TAE<5:0>. This number determines where the background colour of the text area will end if set to extend to the end of the row. It will also terminate the character fetch process thus eliminating the necessity of a row end attribute. This entails however writing to all positions. The vertical offset is set in the MMR Text Position Vertical Register. The offset value VOL<5:0> is done in number of TV scan lines. 1999 Oct 27 61 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 19.12 Video/data switch adjustment To take into account the delay between the RGB values and the VDS signal due to external buffering, the VDS signal can be moved in relation to the RGB signals. The VDS signal can be set to be either a clock cycle before or after the RGB signal, or coincident with the RGB signal. This is done using VDEL<2:0> in the MMR Configuration. 19.13 RGB brightness control A brightness control is provided to allow the RGB upper output voltage level to be modified. The nominal value is 1 V into a 15 resistor, but can be varied between 0.7 and 1.2 V. The brightness is set in the RGB Brightness Register. Table 21 RGB brightness BRI3 TO BRI0 0000 ... 1111 ... highest value RGB BRIGHTNESS lowest value SAA55xx 20 MEMORY MAPPED REGISTERS (MMR) The memory mapped registers are used to control the display. The registers are mapped into the microcontroller MOVX address space, starting at address 87F0H and extending to 87FFH. Table 22 MMR address summary REGISTER NO. 1 2 3 4 7 8 12 13 15 MEMORY ADDRESS 87F1H 87F2H 87F3H 87F4H 87F7H 87F8H 87FCH 87FDH 87FFH FUNCTION Text Position Vertical Text Area Start Fringing Control Text Area End RGB Brightness Status HSYNC Delay VSYNC Delay Configuration 19.14 Contrast reduction The COR bits in SFRs TXT5 and TXT6 control when the COR output of the device is activated (i.e. pulled LOW). This output is intended to act on the TVs display circuits to reduce contrast of the video when it is active. The result of contrast reduction is to improve the readability of the text in a mixed teletext and video display. The bits in the TXT5 and TXT6 SFRs allow the display to be set up so that, for example, the areas inside teletext boxes will be contrast reduced when a subtitle is being displayed but that the rest of the screen will be displayed as normal video. 1999 Oct 27 62 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) Table 23 MMR map ADD R/W 87F1 87F2 87F3 87F4 87F7 87F8 NAME - HOP1 FRC3 - VDSPOL BUSY - - - - 7 - HOP0 FRC2 - - FIELD - HSD6 VSD6 VDEL2 6 5 VOL5 TAS5 FRC1 TAE5 - - - HSD5 VSD5 VDEL1 4 VOL4 TAS4 FRC0 TAE4 - FLR FLR HSD4 VSD4 VDEL0 3 VOL3 TAS3 FRDN TAE3 BRI3 - - HSD3 VSD3 TXT/V 2 VOL2 TAS2 FRDE TAE2 BRI2 - - HSD3 VSD2 - 1 VOL1 TAS1 FRDS TAE1 BRI1 - - HSD1 VSD1 - SAA55xx 0 VOL0 TAS0 FRDW TAE0 BRI0 - - HSD0 VSD0 - RESET 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H R/W Text Position Vertical R/W Text Area Start R/W Fringing Control R/W Text Area End R/W RGB Brightness R W Status 87FC R/W HSYNC Delay 87FD R/W VSYNC Delay 87FF R/W Configuration Table 24 MMR bit definition REGISTER Text Position Vertical VOL5 to VOL0 Text Area Start HOP1 to HOP0 TAS5 to TAS0 Fringing Control FRC3 to FRC0 FRDN FRDE FRDS FRDW Text Area End TAE5 to TAE0 RGB Brightness VDSPOL FUNCTION display start vertical offset from VSYNC (lines) fine horizontal offset in quarter of characters text area start fringing colour, value address of CLUT fringe in north direction (logic 1) fringe in east direction (logic 1) fringe in south direction (logic 1) fringe in west direction (logic 1) text area end, in full characters VDS polarity 0 = RGB (1), Video (0) 1 = RGB (0), Video (1) BRI3 to BRI0 RGB brightness control 1999 Oct 27 63 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) REGISTER Status read BUSY FIELD FLR Status write FLR HSYNC Delay HSD6 to HSD0 VSYNC Delay VSD6 to VSD0 Configuration VDEL2 to VDEL0 pixel delay between VDS and RGB output 000 = VDS switched to video, not active 001 = VDS active one pixel earlier then RGB 010 = VDS synchronous to RGB 100 = VDS active one pixel after RGB TXT/V BUSY signal switch; horizontal (logic 1) VSYNC delay in number of 8-bit 12 MHz clock cycles HSYNC delay, in full size characters active flash region background colour only displayed (logic 1) access to display memory could cause display problems (logic 1) even field (logic 1) active flash region background only displayed (logic 1) FUNCTION SAA55xx 1999 Oct 27 64 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 21 LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 134). SYMBOL VDDX VI VO IO IIOK Tamb Tstg Note PARAMETER supply voltage (all supplies) input voltage (any input) output voltage (any output) output current (each output) DC input or output diode current operating ambient temperature storage temperature note 1 note 1 CONDITIONS MIN. -0.5 -0.5 -0.5 - - -20 -55 +4.0 MAX. SAA55xx UNIT V V V mA mA C C VDD + 0.5 or 4.1 VDD + 0.5 10 20 +70 +125 1. This maximum value refers to 5 V tolerant I/Os and may be 6 V maximum but only when VDD is present. 22 CHARACTERISTICS VDD = 3.3 V 10%; VSS = 0 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDDX IDDP IDDC IDDC(id) IDDC(pd) IDDC(stb) IDDA IDDA(id) IDDA(pd) IDDA(stb) Digital inputs RESET VIL VIH Vhys ILI Rpd LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current equivalent pull-down resistance VI = 0 VI = VDD - 1.49 0.44 - 55.73 - - - - 70.71 1.34 5.5 0.58 0.17 92.45 V V V A k any supply voltage (VDD to VSS) periphery supply current core supply current Idle mode core supply current Power-down mode core supply current Standby mode core supply current analog supply current Idle mode analog supply current Power-down mode analog supply current Standby mode analog supply current note 1 3.0 1 - - - - - - - - 3.3 - 15 4.6 0.76 5.11 45 0.87 0.45 0.95 3.6 - 18 6 1 6.50 48 1 0.7 1.20 V mA mA mA mA mA mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 1999 Oct 27 65 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SYMBOL HSYNC, VSYNC VIL VIH Vhys ILI Digital outputs FRAME, VDS VOL VOH tr tf LOW-level output voltage HIGH-level output voltage output rise time output fall time IOL = 3 mA IOH = 3 mA 10% to 90%; CL = 70 pF 10% to 90%; CL = 70 pF IOL = 3 mA IOL = -3 mA; push-pull - 2.84 7.50 6.70 - - 8.85 7.97 LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current VI = 0 to VDD - 1.44 0.40 - - - - - PARAMETER CONDITIONS MIN. TYP. SAA55xx MAX. UNIT 1.31 5.5 0.56 0.00 V V V A 0.13 - 10.90 10.00 V V ns ns COR (OPEN-DRAIN OUTPUT) VOL VOH VIL VIH ILI tr tf LOW-level output voltage HIGH-level pull-up output voltage LOW-level input voltage HIGH-level input voltage input leakage current output rise time output fall time VI = 0 to VDD 10% to 90%; CL = 70 pF 10% to 90%; CL = 70 pF - 2.84 - 0.00 - 7.20 4.90 - - - - - 8.64 7.34 0.14 - 0.00 5.50 0.12 11.10 9.40 V V V V A ns ns Digital input/outputs P0.0 TO P0.4, P0.7, P1.0 TO P1.1, P2.1 TO P2.7, P3.0 TO P3.7 VIL VIH Vhys ILI VOL VOH tr LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current LOW-level output voltage HIGH-level output voltage output rise time VI = 0 to VDD IOL = 4 mA IOH = -4 mA; push-pull 10% to 90%; CL = 70 pF push-pull 10% to 90%; CL = 70 pF - 1.43 0.41 - - 2.81 6.50 - - - - - - 8.47 1.28 5.50 0.55 0.01 0.18 5.50 10.70 V V V A V V ns tf output fall time 5.70 7.56 10.00 ns 1999 Oct 27 66 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SYMBOL P1.2, P1.3 AND P2.0 VIL VIH Vhys ILI VOL VOH tr LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current LOW-level output voltage HIGH-level output voltage output rise time VI = 0 to VDD IOL = 4 mA IOH = -4 mA; push-pull 10% to 90%; CL = 70 pF; push-pull 10% to 90%; CL = 70 pF - 1.45 0.42 - - 2.81 7.00 - - - - - - 8.47 PARAMETER CONDITIONS MIN. TYP. SAA55xx MAX. UNIT 1.29 5.50 0.56 0.02 0.17 5.50 10.50 V V V A V V ns tf P0.5 AND P0.6 VIL VIH ILI Vhys VOL VOH tr output fall time 5.40 7.36 9.30 ns LOW-level input voltage HIGH-level input voltage input leakage current hysteresis voltage of Schmitt trigger input LOW-level output voltage HIGH-level output voltage output rise time IOL = 8 mA IOH = -8 mA; push-pull 10% to 90%; CL = 70 pF; push-pull 10% to 90%; CL = 70 pF VI = 0 to VDD - 1.43 - 0.42 - 2.76 7.40 - - - - - - 8.22 1.28 5.50 0.11 0.58 0.20 5.50 8.80 V V A V V V ns tf output fall time 4.20 4.57 5.20 ns P1.4 TO P1.7 (OPEN-DRAIN) VIL VIH Vhys ILI VOL tf LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current LOW-level output voltage output fall time VI = 0 to VDD IOL = 8 mA 10% to 90%; CL = 70 pF - 1.62 0.49 - - 69.70 - - - - - 83.67 1.45 5.50 0.60 0.13 0.35 103.30 V V V A V ns 1999 Oct 27 67 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SYMBOL Analog inputs CVBS0 AND CVBS1 Vsync Vvid(p-p) Zsource VIH CI IREF Rgnd ADC0 TO ADC3 VIH CI VPE VIH Analog outputs R, G AND B IOL IOH output current (black Level) output current (maximum Intensity) output current (70% of full Intensity) Rload CL load resistor to VSSA load capacitance VDDA = 3.3 V VDDA = 3.3 V Intensity level code = 15 dec VDDA = 3.3 V Intensity level code = 0 dec resistor tolerance 5% -10 6.0 - 6.67 HIGH-level input voltage - - 9.0 HIGH-level input voltage input capacitance - - - - resistor to ground resistor tolerance 2% - 24 - sync voltage amplitude video input voltage amplitude (peak-to-peak value) source impedance HIGH-level input voltage input capacitance 0.1 0.7 0 3.0 - 0.3 1.0 - - - 0.6 1.4 250 PARAMETER CONDITIONS MIN. TYP. SAA55xx MAX. UNIT V V V pF VDDA + 0.3 10 k VDDA 10 V pF V +10 7.3 A mA 4.2 4.7 5.1 mA - - 150 - - 15 pF Analog input/output SYNC_FILTER Csync Vsync Crystal oscillator XTALIN VIL VIH CI LOW-level input voltage HIGH-level input voltage input capacitance VSSA - - - - - - VDDA 10 V V pF storage capacitor to ground sync filter level voltage for nominal sync amplitude - 0.35 100 0.55 - 0.75 nF V 1999 Oct 27 68 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SYMBOL XTALOUT CO fxtal CL C1 Rr Cosc C0 Txtal Xj Xd Notes 1. Peripheral current is dependent on external components and voltage levels on I/Os. 2. Crystal order number 4322 143 05561. output capacitance - fundamental mode Tamb = 25 C Tamb = 25 C Tamb = 25 C Tamb = 25 C - - - - - - -20 - - - 12 - - note 4 - +25 - - 10 - 30 20 60 - PARAMETER CONDITIONS MIN. TYP. SAA55xx MAX. UNIT pF Crystal specification; notes 2 and 3 nominal frequency crystal load capacitance crystal motional capacitance resonance resistance crystal holder capacitance temperature range adjustment tolerance drift MHz pF fF pF pF C capacitors at XTALIN, XTALOUT Tamb = 25 C note 5 +85 50 x 10-6 100 x 10-6 3. If the 4322 143 05561 crystal is not used, then the formulae in the crystal specification should be used. Where CIO = 7 pF, the mean of the capacitances due to the chip at XTALIN and at XTALOUT. Cext is a value for the mean of the stray capacitances due to the external circuit at XTALIN and XTALOUT. The maximum value for the crystal holder capacitance is to ensure start-up, Cosc may need to be reduced from the initially selected value. 4. Cosc(typ) = 2CL - CIO - Cext 5. C0(max) = 35 - 12(Cosc + CIO + Cext) 1999 Oct 27 69 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 22.1 I2C-bus characteristics SAA55xx Table 25 I2C-bus characteristics FAST-MODE I2C-bus SYMBOL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO Cb Notes 1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIL(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 2. The maximum fHD;DAT has only to be met if the device does not stretch the LOW period tLOW of the SCL signal. 3. A fast-mode I2C-bus device can be used in a standard mode I2C-bus system but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 +1250 ns (according to the standard mode I2C-bus specification) before the SCL line is released. SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition data hold time; notes 1 and 2 data set-up time, note 3 rise time of both SDA and SCL signals fall time of both SDA and SCL signals set-up time for STOP condition capacitive load for each bus line PARAMETER MIN. 0 1.3 0.6 1.3 0.6 0.6 0 100 20 20 0.6 - - - - - - 0.9 - 300 300 - 400 MAX. 400 kHz s s s s s s ns ns ns s pF UNIT 1999 Oct 27 70 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 23 QUALITY AND RELIABILITY SAA55xx This device will meet Philips Semiconductors General Quality Specification for Business group "Consumer Integrated Circuits SNW-FQ-611-Part E". The principal requirements are shown in Tables 26 to 29. 23.1 Group A Table 26 Acceptance tests per lot TEST Mechanical Electrical Note 1. ppm = fraction of defective devices, in parts per million. 23.2 Group B cumulative target: <80 ppm cumulative target: <100 ppm REQUIREMENTS(1) Table 27 Processability tests (by package family) TEST Solderability Mechanical Solder heat resistance 23.3 Group C 0/16 on all lots 0/15 on all lots 0/15 on all lots REQUIREMENTS Table 28 Reliability tests (by process family) TEST Operational life Humidity life CONDITIONS REQUIREMENTS(1) 168 hours at Tj = 150 C <1000 FPM at Tj = 150 C temperature, humidity, bias 1000 hours, <2000 FPM 85 C, 85% RH (or equivalent test) Temperature cycling performance Tstg(min) to Tstg(max) <2000 FPM Note 1. FPM = fraction of devices failing at test condition, in Failures Per Million. Table 29 Reliability tests (by device type) TEST ESD and latch-up CONDITIONS REQUIREMENTS ESD Human body model 100 pF, 1.5 k 2000 V ESD Machine model 200 pF, 0 200 V latch-up 100 mA, 1.5 x VDD (absolute maximum) 1999 Oct 27 71 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Oct 27 Vtune brightness contrast saturation hue volume (L) volume (R) VSS Vafc AV status 24 APPLICATION INFORMATION Philips Semiconductors handbook, full pagewidth Standard TV microcontrollers with On-Screen Display (OSD) 40 V VDD A0 A1 A2 VDD VDD PH2369 VDD 47 F VDD VSS VSS VSS P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 1 2 3 4 5 6 7 8 9 10 11 12 13 VDD 100 nF VSS VSS EEPROM PCF8582E RC SCL SDA VDD VSS 52 51 50 49 48 47 46 45 44 43 42 41 40 P1.5/SDA1 P1.4/SCL1 P1.7/SDA0 P1.6/SCL0 P1.3/T1 P1.2/INT0 P1.1/T0 P1.0/INT1 VDDP RESET XTALOUT XTALIN OSCGND VDDC VSSP VSYNC HSYNC VDS R G B VDDA P3.4/PWM7 COR VPE FRAME VSS MBK980 TV control signals VDD 10 F VDD IR RECEIVER 72 program+ VSS program- VHF-L VHF-H menu TV control signals UHF minus(-) plus(+) VSS VDD 1 k 1 k VSS 100 nF CVBS (IF) CVBS (SCART) 100 nF 100 nF 12 MHz 56 pF VDD 100 nF VDD 47 F VSS VSS field flyback line flyback VSSD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VSSA CVBS0 CVBS1 SYNC_FILTER IREF 24 k VSS SAA55xx 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 VDD 150 VDD to TV's display circuits Preliminary specification VSS SAA55xx Fig.29 Application diagram. Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 25 ELECTROMAGNETIC COMPATIBILITY (EMC) GUIDELINES Optimization of circuit return paths and minimisation of common mode emission will be assisted by using a double sided Printed-Circuit Board (PCB) with low inductance ground plane. On a single sided printed-circuit board a local ground plane under the whole Integrated Circuit (IC) should be present as shown in Fig.30. This should be connected by the widest possible connection back to the printed-circuit board ground connection, and bulk electrolytic decoupling capacitor. It should preferably not connect to other grounds on the way, and no wire links should be present in this connect. The use of wire links increases ground bounce by introducing inductance into the ground. The supply pins can be decoupled at the pin to the ground plane under the IC. This is easily accomplished using surface mount capacitors, which are more effective than leaded components at high frequency. SAA55xx Using a device socket will unfortunately add to the area and inductance of the external bypass loop. A ferrite bead or inductor with resistive characteristics at high frequencies may be utilised in the supply line close to the decoupling capacitor to provide a high impedance. To prevent pollution by conduction onto the signal lines (which may then radiate) signals connected to the VDD supply via a pull-up resistor should not be connected to the IC side of this ferrite component. OSCGND should be connected only to the crystal load capacitors and not to the local or circuit ground. Physical connection distances to associated active devices should be short. Output traces should be routed with close proximity to mutually coupled ground return paths. handbook, full pagewidth GND +3.3 V electrolytic decoupling capacitor (2 F) other GND connections VDDC VDDP VDDA VSSP ferrite beads SM decoupling capacitors (10 to 100 nF) under-IC GND plane GND connection note: no wire links under-IC GND plane VSSC VSSA IC MBK979 Fig.30 Power supply connections for EMC. 1999 Oct 27 73 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 26 PACKAGE OUTLINES SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SAA55xx SOT247-1 seating plane D ME A2 A L A1 c Z e b1 wM (e 1) MH b 52 27 pin 1 index E 1 26 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 47.9 47.1 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73 ISSUE DATE 90-01-22 95-03-11 1999 Oct 27 74 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) SAA55xx LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X 75 76 51 50 ZE A e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3) A1 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.5 1.3 A3 0.25 bp 0.28 0.16 c 0.18 0.12 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o o 16.25 16.25 15.75 15.75 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-12-19 97-08-04 1999 Oct 27 75 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 27 SOLDERING 27.1 Introduction to soldering through-hole mount packages SAA55xx The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 27.3 Manual soldering This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 27.2 Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. 27.4 Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING WAVE suitable(1) DBS, DIP, HDIP, SDIP, SIL Note suitable 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 1999 Oct 27 76 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) 28 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values SAA55xx This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 29 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 30 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Oct 27 77 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) NOTES SAA55xx 1999 Oct 27 78 Philips Semiconductors Preliminary specification Standard TV microcontrollers with On-Screen Display (OSD) NOTES SAA55xx 1999 Oct 27 79 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999 Internet: http://www.semiconductors.philips.com SCA 68 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/01/pp80 Date of release: 1999 Oct 27 Document order number: 9397 750 05048 |
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